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a dsp microcomputer information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringeme nts of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o.box 9106, norwood, ma 02062-9106, u.s.a. tel:781/329-4700 www.analog.com fax:781/326-8703 ? analog devices, inc., 2002 rev. a adsp-2191m performance features 6.25 ns instruction cycle time, for up to 160 mips sustained performance adsp-218x family code compatible with the same easy to use algebraic syntax single-cycle instruction execution single-cycle context switch between two sets of com- putation and memory instructions instruction cache allows dual operand fetches in every instruction cycle multifunction instructions pipelined architecture supports efficient code execution architectural enhancements for compiled c and c++ code efficiency architectural enhancements beyond adsp-218x family are supported with instruction set extensions for added registers, and peripherals flexible power management with user-selectable power-down and idle modes functional block diagram data address b l o c k 3 data address b l o c k 2 2 system interrupt controller i/o data serial ports (3) spi ports (2) 18 i/o registers (memory-mapped) control status buffers i/o processor cache 64 24-bit jtag test & emulation 6 addr bus mux data bus mux 16 22 pm address bus dm address bus pm data bus dm data bus px 24 16 adsp-219x dsp core program sequencer data register file mult barrel shifter alu uart port (1) dma controller 6 input registers result registers 16 16-bit host port 24 dag1 4 4 16 dag2 4 4 16 internal memory 24 24 address b l o c k 1 data data address b l o c k 0 24 bit 16 bit 16 bit four independent blocks programmable flags (16) timers (3) 3 dma connect dma address external port 24 bit 18 i/o address 24 16 24 dma data
adsp-2191m ?2? rev. a integration features 160k bytes on-chip ram configured as 32k words 24-bit memory ram and 32k words 16-bit memory ram dual-purpose 24-bit memory for both instruction and data storage independent alu, multiplier/accumulator, and barrel shifter computational units with dual 40-bit accumulators unified memory space allows flexible address genera- tion, using two independent dag units powerful program sequencer provides zero-overhead looping and conditional instruction execution enhanced interrupt controller enables programming of interrupt priorities and nesting modes system interface features host port with dma capability for glueless 8- or 16-bit host interface 16-bit external memory interf ace for up to 16m words of addressable memory space three full-duplex multichann el serial ports, with support for h.100 and up to 128 tdm channels with a-law and -law companding optimized for telecom- munications systems two spi-compatible ports with dma support uart port with dma support 16 general-purpose i/o pins with integrated interrupt support three programmable interval timers with pwm generation, pwm capture/pulsewidth measurement, and external event counter capabilities up to 11 dma channels can be active at any given time for high i/o throughput on-chip boot rom for automatic booting from external 8- or 16-bit host device, spi rom, or uart with autobaud detection programmable pll supports 1 to 32 input frequency multiplication and can be altered during runtime ieee jtag standard 1149.1 test access port supports on-chip emulation and system debugging 2.5 v internal oper ation and 3.3 v i/o 144-lead lqfp and 144-ball mini-bga packages table of contents general description . . . . . . . . . . . . . . . . . . . . .3 dsp core architecture . . . . . . . . . . . . . . . . . . . . . . . .3 dsp peripherals architecture . . . . . . . . . . . . . . . . . . .4 memory architecture . . . . . . . . . . . . . . . . . . . . . . . . .5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 host port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 dsp serial ports (sports) . . . . . . . . . . . . . . . . . . . .8 serial peripheral interface (spi) ports . . . . . . . . . . . . .9 uart port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 programmable flag (pfx) pins . . . . . . . . . . . . . . . . . .9 low power operation . . . . . . . . . . . . . . . . . . . . . . . .10 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 booting modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 bus request and bus grant . . . . . . . . . . . . . . . . . . .12 instruction set description . . . . . . . . . . . . . . . . . . . .13 development tools . . . . . . . . . . . . . . . . . . . . . . . . . .13 additional information . . . . . . . . . . . . . . . . . . . . . . .15 pin function descriptions . . . . . . . . . . . . . .15 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .18 absolute maximum ratings . . . . . . . . . . .19 esd sensitivity . . . . . . . . . . . . . . . . . . . . . . . . .19 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .19 timing specifications . . . . . . . . . . . . . . . . .20 output drive currents . . . . . . . . . . . . . . . . . . . . . . .40 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .40 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 environmental conditions . . . . . . . . . . . . . . . . . . . .41 144-lead lqfp pinout . . . . . . . . . . . . . . . . . . . . . .43 144-lead mini-bga pinout . . . . . . . . . . . . . . . . . . .45 outline dimensions . . . . . . . . . . . . . . . . . . . . .47 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . .48 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
?3? rev. a adsp-2191m general description the adsp-2191m dsp is a single-chip microcomputer optimized for digital signal pr ocessing (dsp) and other high speed numeric processing applications. the adsp-2191m combines the adsp-219x family base architecture (three computational units, two data address gener- ators, and a program sequencer) with three serial ports, two spi-compatible ports, one uart port, a dma controller, three programmable timers, general-purpose programmable flag pins, extensive interrupt capab ilities, and on-chip program and data memory spaces. the adsp-2191m architecture is code-compatible with dsps of the adsp-218x family. although the architectures are compatible, the adsp-2191m architecture has a number of enhancements over the adsp-2 18x architecture. the enhance- ments to computational units, data address generators, and program sequencer make the adsp-2191m more flexible and even easier to program. indirect addressing options pr ovide addressing flexibility? premodify with no update, pre- and post-modify by an immediate 8-bit, two?s-complement value and base address registers for easier implementation of circular buffering. the adsp-2191m integrates 64k words of on-chip memory configured as 32k words (24-bit) of program ram, and 32k words (16-bit) of data ram. power-down circuitry is also provided to reduce power consumption. the adsp-2191m is available in 144-lead lqfp and 144-ball mini-bga packages. fabricated in a high speed, lo w power, cmos process, the adsp-2191m operates with a 6.25 ns instruction cycle time (160 mips). all instructions, except single-word instructions, execute in one processor. the adsp-2191m?s flexible architecture and comprehensive instruction set support multiple operations in parallel. for example, in one processor cycle, the adsp-2191m can: ? generate an address for th e next instruction fetch ? fetch the next instruction ? perform one or two data moves ? update one or two data address pointers ? perform a computational operation these operations take place while the processor continues to: ? receive and transmit data through two serial ports ? receive and/or transm it data from a host ? receive or transmit data through the uart ? receive or transmit data over two spi ports ? access external memory through the external memory interface ? decrement the timers dsp core architecture the adsp-2191m instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. every single-word instruction can be executed in a single processor cycle. the adsp-2191m assembly language uses an algebraic syntax for ease of coding and readability. a comprehensive set of development tools supports program development. the functional block diagram on page 1 shows the architecture of the adsp-219x core. it contains three independent compu- tational units: the alu, the multiplier/accumulator (mac), and the shifter. the computational un its process 16-bit data from the register file and have provisions to support multiprecision com- putations. the alu performs a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add, and multi- ply/subtract operations. the mac has two 40-bit accumulators, which help with overflow. the shifter performs logical and arith- metic shifts, normalization, denormalization, and derive exponent operations. the shifte r can be used to efficiently implement numeric format control, including multiword and block floating-point representations. register-usage rules influence placement of input and results within the computational units. for most operations, the com- putational units? data registers act as a data register file, permitting any input or result register to provide input to any unit for a computation. for feedback operations, the computational units let the output (result) of any unit be input to any unit on the next cycle. for conditional or multifunction instructions, there are restrictions on which da ta registers may provide inputs or receive results from each co mputational unit. for more infor- mation, see the adsp-219x dsp instruction set reference . a powerful program sequencer controls the flow of instruction execution. the sequencer supports conditional jumps, subrou- tine calls, and low interrupt overhead. with internal loop counters and loop stacks, the adsp-2191m executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four 16-bit address pointers. whenever the pointer is used to access data (indirect addressing), it is pre- or post-modified by the value of one of four possible modify registers. a length value and base address may be associated with each pointer to implement automatic modulo addressing for circular buffers. page registers in the dags allow circular addressing within 64k-word bound- aries of each of the 256 memory pages, but these buffers may not cross page boundaries. secondary registers duplicate all the primary registers in the dags; switching between primary and secondary registers provides a fast context switch. efficient data transfer in the core is achieved with the use of internal buses: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? dma address bus ? dma data bus
adsp-2191m ?4? rev. a the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd and dmd) share a single external data bus. boot memory space and i/o memory space also share the external buses. program memory can store both instructions and data, permit- ting the adsp-2191m to fetch two operands in a single cycle, one from program memory and one from data memory. the dsp?s dual memory buses also let the adsp-219x core fetch an operand from data memory an d the next instruction from program memory in a single cycle. dsp peripherals architecture the functional block diagram on page 1 shows the dsp?s on-chip peripherals, which include the external memory inter- face, host port, serial ports, spi-compatible ports, uart port, jtag test and emulation port, timers, flags, and interrupt con- troller. these on-chip peripherals can connect to off-chip devices as shown in figure 1 . the adsp-2191m has a 16-bit ho st port with dma capability that lets external hosts access on-chip memory. this 24-pin parallel port consists of a 16-pin multiplexed data/address bus and provides a lowservice overhead data move capability. con- figurable for 8 or 16 bits, this port provides a glueless interface to a wide variety of 8- and 16-bit microcontrollers. two chip-selects provide hosts access to the dsp?s entire memory map. the dsp is bootable through this port. the adsp-2191m also has an extern al memory interface that is shared by the dsp?s core, the dma controller, and dma capable peripherals, which include the uart, sport0, sport1, sport2, spi0, spi1, and the host port. the external port consists of a 16-bit data bus, a 22-bit address bus, and control signals. the data bus is configurable to provide an 8- or 16-bit interface to external me mory. support for word packing lets the dsp access 16- or 24-bit words from external memory regardless of the external data bus width. when configured for an 8-bit interface, the unused eight lines provide eight program- mable, bidirectional general-pu rpose programmable flag lines, six of which can be mapped to software condition signals. the memory dma controller le ts the adsp-2191m move data and instructions from between memory spaces: internal-to-exter- nal, internal-to-internal, and external-to-external. on-chip peripherals can also use this controller for dma transfers. the adsp-2191m can respond to up to seventeen interrupts at any given time: three internal (stack, emulator kernel, and power-down), two external (emulator and reset), and twelve user- defined (peripherals) interrupts. the programmer assigns a peripheral to one of the 12 user-d efined interrupts. the priority of each peripheral for interrupt service is determined by these assignments. there are three serial ports on the adsp-2191m that provide a complete synchronous, full-duplex serial interface. this interface includes optional companding in hardware as well as a wide variety of framed or frameless data transmit and receive modes of operation. each serial port can transmit or receive an internal or external, programmable serial clock and frame syncs. each serial port supports 128-channe l time division multiplexing. the adsp-2191m provides up to sixteen general-purpose i/o pins, which are programmable as either inputs or outputs. eight of these pins are dedicated-ge neral purpose programmable flag pins. the other eight of them are multifunctional pins, acting as general-purpose i/o pins when the dsp connects to an 8-bit external data bus and acting as the upper eight data pins when the dsp connects to a 16-bit external data bus. these program- mable flag pins can implement edge- or level-sensitive interrupts, some of which can be used to base the execution of conditional instructions. figure 1. system diagram serial device (optional) data15?8 ioms dsp211m bms ms3C0 br bg c wr rd ddr210 dt0 dt1 ddr210 dt0 cs c we oe eterl memor (optiol) dt1 ddr210 dt0 cs c we oe boot memor (optiol) dt1 ddr10 dt0 cs c we oe eterl io memor (optiol) d d r e s s c o t r o l d t ddr10 dt10 ddr1 cs1 c wr rd host processor (optiol) cs0 le hd10 h1 hcms hcioms hrd hwr hc hle hcp tcl0 ts0 dt0 rcl0 rs0 dr0 tcl1 ts1 dt1 rcl1 rs1 dr1 tcl2sc0 ts2mosi0 dt2miso0 rcl2sc1 rs2mosi1 dr2miso1 rd td reset tg sport1 sport2 sport0 cli tl msel0p0 dp bpss bmode10 opmode clout tmr20 urt spi0 spi1 seril deice (o ptiol) seril deice (o ptiol) urt deice (o ptiol) cloc or crstl timer out or cpture cloc multipl d rge boot d op mode bgh
?5? rev. a adsp-2191m three programmable interval timers generate periodic inter- rupts. each timer can be independently set to operate in one of three modes: ? pulse waveform generation mode ? pulsewidth count/capture mode ? external event watchdog mode each timer has one bidirectional pin and four registers that implement its mode of operation: a 7-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulsewidth register. a single st atus register supports all three timers. a bit in each timer?s configuration register enables or disables the corresponding timer independently of the others. memory architecture the adsp-2191m dsp provides 64k words of on-chip sram memory. this memory is divided into four 16k blocks located on memory page 0 in the dsp?s memory map. in addition to the internal and external memory space, the adsp-2191m can address two additional and separate off-chip memory spaces: i/o space and boot space. as shown in figure 2 , the dsp?s two internal memory blocks populate all of page 0. the entire dsp memory map consists of 256 pages (pages 0 ? 255), and each page is 64k words long. external memory space consists of four memory banks (banks 0?3) and supports a wide variety of sram memory devices. each bank is selectable using the memory select pins ( ms3C0 ) and has configurable page boundaries, waitstates, and waitstate modes. the 1k word of on-chip boot-rom populates the top of page 255 while the remaining 254 pages are addressable off-chip. i/o memory pages differ from external memory pages in that i/o pages are 1k word long, and the external i/o pages have their own select pin ( ioms ). pages 0?7 of i/o memory space reside on-chip and contain the configuration registers for the peripher- als. both the core and dma-ca pable peripherals can access the dsp?s entire memory map. internal (on-chip) memory the adsp-2191m?s unified program and data memory space consists of 16m locations that are accessible through two 24-bit address buses, the pma and dma buses. the dsp uses slightly different mechanisms to generate a 24-bit address for each bus. the dsp has three functions that support access to the full memory map. ? the dags generate 24-bit addresses for data fetches from the entire dsp memory address range. because dag index (address) registers are 16 bits wide and hold the lower 16 bits of the address, each of the dags has its own 8-bit page register (dmpgx) to hold the most significant eight address bits. before a dag generates an address, the program must set the dag?s dmpgx register to the appropriate memory page. ? the program sequencer generates the addresses for instruction fetches. for relative addressing instructions, the program sequencer bases ad dresses for relative jumps, calls, and loops on the 24-bit program counter (pc). in direct addressing instructions (two-word instructions), figure 2. memory map bank2 (ms2) b1 (ms1) b0 (ms0) bloc0 2bit bloc2 1bit bloc1 2bit bloc3 1bit resered boot rom 2bit 0x00 000 0x00 000 0x01 0000 0x0 0000 0x0 0000 0xc0 0000 0x 0000 0x 000 0x logicl ddress word memor pges pge 0 pges 13 pges 12 pges 1211 pges 122 pge 2 iterl memor eterl memor (1bit) iterl memor memor selects (ms) or portios o the memor mp pper with the selected memor pges 12 0x01 0000 0xe io memor 1bit 1 word pges 2 1 word pges 0 lower pge boudries re coigurble or bs o eterl memor boudries show re b sies t reset 0x0 3 0x0 000 0x 3 iterl eterl (ioms) 0x00 0000 0x00 c000 0x 03 0x00 000 bit 10bit boot memor 1bit (bms) word logicl ddress logicl ddress b3 (ms3)
adsp-2191m ?6? rev. a the instruction provides an immediate 24-bit address value. the pc allows linear ad dressing of the full 24-bit address range. ? for indirect jumps and ca lls that use a 16-bit dag address register for part of the branch address, the program sequencer relies on an 8-bit indirect jump page (ijpg) register to supply the most significant eight address bits. before a cross pa ge jump or call, the program must set the program sequencer ?s ijpg register to the appropriate memory page. the adsp-2191m has 1k word of on-chip rom that holds boot routines. if peripheral booting is selected, the dsp starts executing instructions from the on-chip boot rom, which starts the boot process from the selected peripheral. for more informa- tion, see ?booting modes? on page 11. the on-chip boot rom is located on page 255 in the dsp?s memory space map. external (off-chip) memory each of the adsp-2191m?s off- chip memory spaces has a separate control register, so applications can configure unique access parameters for each space. the access parameters include read and write wait counts, waitstate completion mode, i/o clock divide ratio, write hold time extension, strobe polarity, and data bus width. the core clock and peripheral clock ratios influence the external memory access strobe widths. for more information, see ?clock signals? on page 11. the off-chip memory spaces are: ? external memory space ( ms3C0 pins) ? i/o memory space ( ioms pin) ? boot memory space ( bms pin) all of these off-chip memory sp aces are accessible through the external port, which can be co nfigured for data widths of 8 or 16 bits. external memory space external memory space consists of four memory banks. these banks can contain a configurable number of 64k word pages. at reset, the page boundaries fo r external memory have bank0 containing pages 1 ? 63, bank1 containing pages 64 ? 127, bank2 containing pages 128 ? 191, and bank3 that contains pages 192 ? 254. the ms3C0 memory bank pins select banks 3?0, respectively. the external memory interface is byte-addressable and decodes the 8 msbs of the dsp program address to select one of the four banks. both th e adsp-219x core and dma-capa- ble peripherals can access the dsp?s external memory space. i/o memory space the adsp-2191m supports an additional external memory called i/o memory space. this space is designed to support simple connections to peripheral s (such as data converters and external registers) or to bus interface asic data registers. i/o space supports a total of 256k lo cations. the first 8k addresses are reserved for on-chip peripherals. the upper 248k addresses are available for external peripheral devices. the dsp?s instruc- tion set provides instructions for accessing i/o space. these instructions use an 18-bit address that is assembled from an 8-bit i/o page (iopg) register and a 10-bit immediate value supplied in the instruction. both the adsp-219x core and a host (through the host port interfa ce) can access i/o memory space. boot memory space boot memory space consists of on e off-chip bank with 63 pages. the bms memory bank pin selects boot memory space. both the adsp-219x core and dma-ca pable peripherals can access the dsp?s off-chip boot memory space. after reset, the dsp always starts executing instructions from the on-chip boot rom. depending on the boot configuration, the boot rom code can start booting the dsp from boot memory. for more information, see ?booting modes? on page 11. interrupts the interrupt controller lets th e dsp respond to 17 interrupts with minimum overhead. the controller implements an interrupt priority scheme as shown in table 1 . applications can use the unassigned slots for software and peripheral interrupts. table 2 shows the id and priority at reset of each of the periph- eral interrupts. to assign the peripheral interrupts a different priority, applications write the ne w priority to their correspond- ing control bits (determined by their id) in the interrupt priority control register. the peripheral interrupt?s position in the imask and irptl register and its vector address depend on its priority level, as shown in table 1 . because the imask and irptl registers are limited to 16 bits, any peripheral interrupts assigned a priority level of 11 are aliased to the lowest priority bit position (15) in these registers and share vector address 0x00 01e0. table 1. interrupt priorities/addresses interrupt imask/ irptl vector address 1 1 these interrupt vectors start at address 0x10000 when the dsp is in ?no-boot,? run from external memory mode. emulator (nmi)? highest priority na na reset (nmi) 0 0x00 0000 power-down (nmi) 1 0x00 0020 loop and pc stack 2 0x00 0040 emulation kernel 3 0x00 0060 user assigned interrupt 4 0x00 0080 user assigned interrupt 5 0x00 00a0 user assigned interrupt 6 0x00 00c0 user assigned interrupt 7 0x00 00e0 user assigned interrupt 8 0x00 0100 user assigned interrupt 9 0x00 0120 user assigned interrupt 10 0x00 0140 user assigned interrupt 11 0x00 0160 user assigned interrupt 12 0x00 0180 user assigned interrupt 13 0x00 01a0 user assigned interrupt 14 0x00 01c0 user assigned interrupt? lowest priority 15 0x00 01e0
?7? rev. a adsp-2191m interrupt routines can either be ne sted with higher priority inter- rupts taking precedence or processed sequentially. interrupts can be masked or unmasked with the imask register. individual interrupt requests are logically anded with the bits in imask; the highest priority unmasked in terrupt is then selected. the emulation, power-down, and reset interrupts are nonmaskable with the imask register, but software can use the dis int instruction to mask the power-down interrupt. the interrupt control (icntl) register controls interrupt nesting and enables or disables interrupts globally. the general-purpose programmable flag (pfx) pins can be con- figured as outputs, can implement software interrupts, and (as inputs) can implement hardware interrupts. programmable flag pin interrupts can be configured for level-sensitive, single edge-sensitive, or dual edge-sensitive operation. the irptl register is used to force and clear interrupts. on- chip stacks preserve the proces sor status and are automatically maintained during interrupt hand ling. to support interrupt, loop, and subroutine nesting, the pc stack is 33 levels deep, the loop stack is eight levels deep, and the status stack is 16 levels deep. to prevent stack overflow, the pc stack can generate a stack-level interrupt if the pc stack falls below three locations full or rises above 28 locations full. the following instructions global ly enable or disable interrupt servicing, regardless of the state of imask. ena int; dis int; at reset, interrupt servicing is disabled. for quick servicing of interrupts, a secondary set of dag and computational registers exist. switching between the primary and secondary registers lets programs quickly service interrupts, while preserving the dsp?s state. dma controller the adsp-2191m has a dma co ntroller that supports automated data transfers with minimal overhead for the dsp core. cycle stealing dma transfers can occur between the adsp-2191m?s internal memory and any of its dma-capable peripherals. additionally, dma transfers can be accomplished between any of the dma-capabl e peripherals and external devices connected to the external memory interface. dma-capa- ble peripherals include the host port, sports, spi ports, and uart. each individual dma-capa ble peripheral has a dedicated dma channel. to describe each dma sequence, the dma con- troller uses a set of parameters?called a dma descriptor. when successive dma sequences are needed, these dma descriptors can be linked or chained together , so the completion of one dma sequence auto-initiates and starts the next sequence. dma sequences do not contend for bus access with the dsp core; instead dmas ?steal? cycles to access memory. all dma transfers use the dma bus shown in the functional block diagram on page 1 . because all of the peripherals use the same bus, arbitration for dma bus access is needed. the arbi- tration for dma bus access appears in table 4 . host port the adsp-2191m?s host port functions as a slave on the external bus of an external host. the host port interface lets a host read from or write to the dsp?s memory space, boot space, or internal i/o space. examples of hosts include external micro- controllers, microprocessors, or asics. the host port is a multiplexed address and data bus that provides both an 8-bit and a 16-bit data path and operates using an asyn- chronous transmission protocol. through this port, an off-chip table 2. peripheral interrupts and priority at reset interrupt id reset priority slave dma/host port interface 0 0 sport0 receive 1 1 sport0 transmit 2 2 sport1 receive 3 3 sport1 transmit 4 4 sport2 receive/spi0 5 5 sport2 transmit/spi1 6 6 uart receive 7 7 uart transmit 8 8 timer 0 9 9 timer 1 10 10 timer 2 11 11 programmable flag a (any pfx) 12 11 programmable flag b (any pfx) 13 11 memory dma port 14 11 table 3. interrupt control (icntl) register bits bit description 0?3 reserved 4 interrupt nesting enable 5 global interrupt enable 6 reserved 7 mac-biased rounding enable 8?9 reserved 10 pc stack interrupt enable 11 loop stack interrupt enable 12?15 reserved table 4. i/o bus arbitration priority dma bus master arbitration priority sport0 receive dma 0?highest sport1 receive dma 1 sport2 receive dma 2 sport0 transmit dma 3 sport1 transmit dma 4 sport2 transmit dma 5 spi0 receive/transmit dma 6 spi1 receive/transmit dma 7 uart receive dma 8 uart transmit dma 9 host port dma 10 memory dma 11?lowest
adsp-2191m ?8? rev. a host can directly access the dsp?s entire memory space map, boot memory space, and internal i/o space. to access the dsp?s internal memory space, a host steals one cycle per access from the dsp. a host access to the dsp?s external memory uses the external port interface and does not stall (or steal cycles from) the dsp?s core. because a host can access internal i/o memory space, a host can control any of the dsp?s i/o mapped peripherals. the host port is most efficien t when using the dsp as a slave and uses dma to automate the incrementing of addresses for these accesses. in this case, an address does not have to be trans- ferred from the host for every data transfer. host port acknowledge (hack) modes the host port supports a number of modes (or protocols) for generating a hack output for the host. the host selects ack or ready modes using the hack_p and hack pins. the host port also supports two modes for address control: address latch enable (ale) and address cycle control (acc) modes. the dsp auto-detects ale versus acc mode from the hale and hwr inputs. the host por t hack signal polar ity is selected (only at reset) as active high or active low, depending on the value driven on the hack_p pin.the hack polarity is stored into the host port configuration register as a read only bit. the dsp uses hack to indicate to the host when to complete an access. for a read transaction, a host can proceed and complete an access when valid data is present in the read buffer and the host port is not busy doing a write. for a write transac- tions, a host can complete an access when the write buffer is not full and the host port is not busy doing a write. two mode bits in the host port configuration register hpcr [7:6] define the functionality of the hack line. hpcr6 is ini- tialized at reset based on the values driven on hack and hack_p pins (shown in table 5 ); hpcr7 is always cleared (0) at reset. hpcr [7:6] can be modified after reset by a write access to the host port configuration register. the functional modes selected by hpcr [7:6] are as follows (assuming active high signal): ? ?acknowledge is active on strobes; hack goes high from the leading edge of the strobe to indicate when the access can complete. after the host samples the hack active, it can complete the access by removing the strobe.the host port then removes the hack. ? ? r e a d y a c t i v e o n s t r o b e s , g o e s l o w t o i n s e r t waitstate during the access. if the host port cannot complete the access, it dea sserts the hack/ready line. in this case, the host has to extend the access by keeping the strobe asserted. when the host samples the hack asserted, it can then proceed and complete the access by deasserting the strobe. while in address cycle control (acc) mode and the ack or ready acknowledge modes, the hack is returned active for any address cycle. host port chip selects there are two chip-select signals associated with the host port: hcms and hcioms . the host chip memory select ( hcms ) lets the host select the dsp a nd directly access the dsp?s inter- nal/external memory space or boot memory space. the host chip i/o memory select ( hcioms ) lets the host select the dsp and directly access the dsp? s internal i/o memory space. before starting a direct access, the host configures host port interface registers, specifying the width of external data bus (8- or 16-bit) and the target addr ess page (in the ijpg register). the dsp generates the needed memory select signals during the access, based on the target addr ess. the host port interface combines the data from one, two, or three consecutive host accesses (up to one 24-bit value) into a single dma bus access to prefetch host direct reads or to post direct writes. during assembly of larger words, the host port interface asserts ack for each byte access that does not start a read or complete a write. otherwise, the host port interface asserts ack when it has completed the memory access successfully. dsp serial ports (sports) the adsp-2191m incorporates three complete synchronous serial ports (sport0, sport1, and sport2) for serial and multiprocessor communications. the sports support the following features: ? bidirectional operation?ea ch sport has independent transmit and receive pins. ? double-buffered transmit an d receive ports?each port has a data register for transferring data words to and from memory and shift registers for shifting data in and out of the data registers. ? clocking?each transmit and r eceive port can either use an external serial clock ( 40 mhz) or generate its own, in frequencies ranging from 19 hz to 40 mhz. ? word length?each sport supports serial data words from 3 to 16 bits in length transferred in big endian (msb) or little endian (lsb) format. table 5. host port acknowledge mode selection values driven at reset hpcr [7:6] initial values acknowledge mode hack_p hack bit 7 bit 6 0 0 0 1 ready mode 0100ack mode 1000ack mode 1 1 0 1 ready mode
?9? rev. a adsp-2191m ? framing?each transmit and recei ve port can run with or without frame sync signals for each data word. frame sync signals can be generated internally or externally, active high or low, and with either of two pulsewidths and early or late frame sync. ? companding in hardware?each sport can perform a-law or -law companding according to itu recommen- dation g.711. companding can be selected on the transmit and/or receive ch annel of the sport without additional latencies. ? dma operations with single-cycle overhead?each sport can automatically recei ve and transmit multiple buffers of memory data, one data word each dsp cycle. either the dsp?s core or a host processor can link or chain sequences of dma transfers between a sport and memory. the chained dma can be dynamically allocated and updated through the dma descriptors (dma transfer parameters) that set up the chain. ? interrupts?each tran smit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through dma. ? multichannel capability?each sport supports the h.100 standard. serial peripheral interface (spi) ports the dsp has two spi-compatible ports that enable the dsp to communicate with multiple spi-co mpatible devices. these ports are multiplexed with sport2, so either sport2 or the spi ports are active, depending on the state of the opmode pin during hardware reset. the spi interface uses three pins for transferring data: two data pins (master output-slave input, mosix, and master input-slave output, misox) and a clock pin (serial clock, sckx). two spi chip select input pins ( spissx ) let other spi devices select the dsp, and fourteen spi chip select output pins (spixsel7?1) let the dsp select other spi devices. the spi select pins are reconfigured programmable flag pins. using these pins, the spi ports provide a full duplex, synchronous serial interface, which supports both master and slave modes and mul- timaster environments. each spi port?s baud rate and clock phase/polarities are program- mable (see equation below for spi clock rate calculation), and each has an integrated dma cont roller, configurable to support both transmit and receive data streams. the spi?s dma control- ler can only service unidirectional accesses at any given time. during transfers, the spi ports simultaneously transmit and receive by serially shifting data in and out on their two serial data lines. the serial clock line synchr onizes the shifting and sampling of data on the two serial data lines. uart port the uart port provides a simplified uart interface to another peripheral or host. it performs full duplex, asynchronous transfers of serial data. options for the uart include support for 5?8 data bits; 1 or 2 stop bits; and none, even, or odd parity. the uart port supports two modes of operation: ? programmed i/o the dsp?s core sends or receives data by writing or reading i/o-mapped thr or rb r registers, respectively. the data is double-buffered on both transmit and receive. ? dma (direct memory access) the dma controller transfers both transmit and receive data. this reduces the number and frequency of inter- rupts required to transfer data to and from memory. the uart has two dedicated dma channels. these dma channels have lower priority than most dma channels because of their relatively low service rates. the uart?s baud rate (see following equation for uart clock rate calculation), serial data format, error code generation and status, and interrupts are programmable: ? supported bit rates range from 9.5 bits to 5m bits per second (80 mhz peripheral clock). ? supported data formats are 7- to 12-bit frames. ? transmit and receive status ca n be configured to generate maskable interrupts to the dsp?s core. the timers can be used to provide a hardware-assisted autobaud detection mechanism for the uart interface. where d is the programmable divisor = 1 to 65536. programmable flag (pfx) pins the adsp-2191m has 16 bidirectional, general-purpose i/o, programmable flag (pf15?0) pins. the pf7?0 pins are dedicated to general-purpose i/o. the pf15?8 pins serve either as general-purpose i/o pins (if the dsp is connected to an 8-bit external data bus) or serve as data15?8 lines (if the dsp is connected to a 16-bit external da ta bus). the programmable flag pins have special functions for clock multiplier selection and for spi port operation. for more information, see serial peripheral spi clock rate hclk 2 spibaud -------------------------------------- = uart clock rate hclk 16 d ------------------ =
adsp-2191m ?10? rev. a interface (spi) ports on page 9 and clock signals on page 11 . ten memory-mapped registers cont rol operation of the program- mable flag pins: ? flag direction register specifies the direction of each individual pfx pin as input or output. ? flag control and status registers specify the value to drive on each indi vidual pfx output pin. as input, software can predicate instruction execution on the value of individual pfx input pins captured in this register. on e register sets bits, and one register clears bits. ? flag interrupt mask registers enable and disable each individual pfx pin to function as an interrupt to the dsp?s co re. one register sets bits to enable interrupt function, and one register clears bits to disable interrupt function. input pfx pins function as hardware interrupts, and output pfx pins function as software interrupts?latching in the imask and irptl registers. ? flag interrupt polarity register specifies the polarity (active high or low) for interrupt sensitivity on each individual pfx pin. ? flag sensitivity registers specify whether individual pfx pins are level- or edge-sensitive and specify?i f edge-sensitive?whether just the rising edge or both the rising and falling edges of the signal are significant. one register selects the type of sensitivity, and one register selects which edges are signif- icant for edge-sensitivity. low power operation the adsp-2191m has four low power options that significantly reduce the power dissipation when the device operates under standby conditions. to enter any of these modes, the dsp executes an idle instruction. the adsp-2191m uses configu- ration of the pdwn, stopck, and stopall bits in the pllctl register to select between the low power modes as the dsp executes the idle. depending on the mode, an idle shuts off clocks to different parts of the dsp in the different modes. the low power modes are: ? idle ? power-down core ? power-down core/peripherals ? power-down all idle mode when the adsp-2191m is in idle mode, the dsp core stops executing instructions, retains the contents of the instruction pipeline, and waits for an interrup t. the core clock and peripheral clock continue running. to enter idle mode, the dsp can execute the idle instruction anywhere in code. to exit idle mode, the dsp responds to an interrupt and (after two cycles of latency) resumes executing instructions with the instruction after the idle. power-down core mode when the adsp-2191m is in power-down core mode, the dsp core clock is off, but the dsp retains the contents of the pipeline and keeps the pll running. the pe ripheral bus keeps running, letting the peripherals receive data. to enter power-down core mode, the dsp executes an idle instruction after performing the following tasks: ? enter a power-down interrupt service routine ? check for pending interrupts and i/o service routines ? clear (= 0) the pdwn bit in the pllctl register ? clear (= 0) the stopall bit in the pllctl register ? set (= 1) the stopck bit in the pllctl register to exit power-down core mode, the dsp responds to an interrupt and (after two cycles of latency) resumes executing instructions with the instruction after the idle. power-down core/peripherals mode when the adsp-2191m is in power-down core/peripherals mode, the dsp core clock and peripheral bus clock are off, but the dsp keeps the pll running. the dsp does not retain the contents of the instruction pipeline.the peripheral bus is stopped, so the peripherals cannot receive data. to enter power-down core/peripherals mode, the dsp executes an idle instruction after performing the following tasks: ? enter a power-down interrupt service routine ? check for pending interrupts and i/o service routines ? clear (= 0) the pdwn bit in the pllctl register ? set (= 1) the stopall bit in the pllctl register to exit power-down core/perip herals mode, the dsp responds to a wake-up event and (after five to six cycles of latency) resumes executing instructions with the instruction after the idle. power-down all mode when the adsp-2191m is in power-down all mode, the dsp core clock, the peripheral clock, and the pll are all stopped. the dsp does not retain the contents of the instruction pipeline. the peripheral bus is stopped, so the peripherals cannot receive data. to enter power-down all mode, the dsp executes an idle instruction after performing the following tasks: ? enter a power-down interrupt service routine ? check for pending interrupts and i/o service routines ? set (= 1) the pdwn bit in the pllctl register to exit power-down core/perip herals mode, the dsp responds to an interrupt and (after 500 cycles to restabilize the pll) resumes executing instructions with the instruction after the idle.
?11? rev. a adsp-2191m clock signals the adsp-2191m can be clocked by a crystal oscillator or a buffered, shaped clock derived from an external clock oscillator. if a crystal oscillator is used, the crystal should be connected across the clkin and xtal pins , with two capacitors and a 1m ? shunt resistor connected as shown in figure 3 . capacitor values are dependent on crystal ty pe and should be specified by the crystal manufacturer. a parallel-resonant, fundamental fre- quency, microprocessor-grade crystal should be used for this configuration. if a buffered, shaped clock is used, this external clock connects to the dsp?s clkin pin. clkin input cannot be halted, changed, or operated below the specified frequency during normal operation. when an external clock is used, the xtal input must be left unconnected. the dsp provides a user-programmable 1 to 32 multiplica- tion of the input clock, including some fractional values, to support 128 external to internal (dsp core) clock ratios. the msel6?0, bypass, and df pins decide the pll multiplication factor at reset. at runtime, the multiplication factor can be con- trolled in software. the combination of pullup and pull-down resistors in figure 3 sets up a core clock ratio of 6:1, which produces a 150 mhz core clock from the 25 mhz input. for other clock multiplier settings, see the adsp-219x/adsp-2191 dsp hardware reference . the peripheral clock is supplied to the clkout pin. all on-chip peripherals for the adsp-2191m operate at the rate set by the peripheral clock. the peripheral clock is either equal to the core clock rate or one-ha lf the dsp core clock rate. this selection is controlled by the io sel bit in the pllctl register. the maximum core clock is 160 mhz and the maximum periph- eral clock is 80 mhz?the combination of the input clock and core/peripheral clock ratios may not exceed these limits. reset the reset signal initiates a master reset of the adsp-2191m. the reset signal must be asserted during the powerup sequence to assure proper initialization. reset during initial powerup must be held long enough to allow the internal clock to stabilize. the powerup sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid v dd is applied to the processor, and for the inte rnal phase-locked loop (pll) to lock onto the specific crystal frequency. a minimum of 100 s ensures that the pll has locked, but does not include the crystal oscillator start-up time. during this powerup sequence the reset signal should be held low. on any subsequent resets, the reset signal must meet the minimum pulsewidth specifica- tion, t wrst . the reset input contains some hysteresis. if using an rc circuit to generate your reset signal, the circuit should use an external schmidt trigger. the master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and resets all registers to their default values (where applicable). when reset is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. program control jumps to the location of the on-chip boot rom (0xff 0000). power supplies the adsp-2191m has separate po wer supply connections for the internal (v ddint ) and external (v ddext ) power supplies. the internal supply must meet the 2.5 v requirement. the external supply must be connected to a 3.3 v supply. all external supply pins must be connected to the same supply. power-up sequence power up together the two supplies v ddext and v ddint . if they cannot be powered up together, power up the internal (core) supply first (powering up the core supply first reduces the risk of latchup events. booting modes the adsp-2191m has five mechanisms (listed in table 6 ) for automatically loading internal program memory after reset. two no-boot modes are also supported. figure 3. external crystal connections clkin clkout xtal adsp-2196m msel5 (pf5) msel4 (pf4) msel3 (pf3) msel2 (pf2) msel1 (pf1) msel0 (pf0) reset 2mh msel (p) d (p) dd dd bpss reset source rutime p pi io the pulluppulldow resistors o the msel d d bpss pis select the core cloc rtio here the selectio (1) d 2mh iput cloc produce 10mh core cloc 1m
adsp-2191m ?12? rev. a the opmode, bmode1, and bmode0 pins, sampled during hardware reset, and three bits in the reset configuration register implement these modes: ? execute from memory external 16 bits?the memory boot routine located in boot rom memory space executes a boot-str eam-formatted program located at address 0x010000 of boot memory space, packing 16-bit external data into 24-bit internal data. the external port interface is configured for the default clock multiplier (128) and read waitstates (7). ? boot from eprom?the eprom boot routine located in boot rom memory space fetches a boot-stream-for- matted program located at physical address 0x00 0000 of boot memory space, packing 8- or 16-bit external data into 24-bit internal data. the external port interface is configured for the default cl ock multiplier (32) and read waitstates (7). ? boot from host?the (8- or 16-bit) host downloads a boot-stream-formatted program to internal or external memory. the host?s boot rout ine is located in internal rom memory space and uses the top 16 locations of page 0 program memory and the top 272 locations of page 0 data memory. the internal boot rom sets semaphore a (an io register within the host port) and then polls until the semaphore is reset. once detected, the in ternal boot rom will remap the interrupt vector table to page 0 internal memory and jump to address 0x00 0000 internal memory. from the point of view of the host inte rface, an external host has full control of the dsp?s memo ry map. the host has the freedom to directly write internal memory, external memory, and internal i/o me mory space. the dsp core execution is held off until th e host clears the semaphore register. this strategy allows the maximum flexibility for the host to boot in the program and data code, by leaving it up to the programmer. ? execute from memory external 8 bits (no boot)? execution starts from page 1 of external memory space, packing either 8- or 16-bit external data into 24-bit internal data. the external port interface is config- ured for the default clock multiplier (128) and read waitstates (7). ? boot from uart?using an autobaud handshake sequence, a boot-stream-formatted program is down- loaded by the host. the host agent selects a baud rate within the uart?s clocking ca pabilities. after a hardware reset, the dsp?s uart expect s a 0xaa character (eight bits data, one start bit, one stop bit, no parity bit) on the rxd pin to determine the bit rate; and then replies with an ok string. once the host r eceives this ok it downloads the boot stream without further handshake.the uart boot routine is located in internal rom memory space and uses the top 16 locations of page 0 program memory and the top 272 locations of page 0 data memory. ? boot from spi, up to 4k bits?the spi0 port uses the spi0sel1 (reconfigured pf2) output pin to select a single serial eeprom device, submits a read command at address 0x00, and begins cl ocking consecutive data into internal or external memory . use only spi-compatible eeproms of 4k bit (12-bit address range). the spi0 boot routine located in in ternal rom memory space executes a boot-stream-format ted program, using the top 16 locations of page 0 prog ram memory and the top 272 locations of page 0 data memory. the spi boot configu- ration is spibaud0=60 (decimal), cpha=1, cpol=1, 8-bit data, and msb first. ? boot from spi, from >4k bi ts to 512k bits?the spi0 port uses the spi0sel1 (re- configured pf2) output pin to select a single serial ee prom device, submits a read command at address 0x00, an d begins clocking consecu- tive data into internal or external memory. use only spi-compatible eeproms of 4k bit (16-bit address range). the spi0 boot routin e, located in internal rom memory space, executes a boot-stream-formatted program, using the top 16 locations of page 0 program memory and the top 272 locations of page 0 data memory. as indicated in table 6 , the opmode pin has a dual role, acting as a boot mode select during reset and determining sport or spi operation at runtime. if th e opmode pin at reset is the opposite of what is needed in an application during runtime, the application needs to set the op mode bit appropriately during runtime prior to using the corresponding peripheral. bus request and bus grant the adsp-2191m can relinquish control of the data and ad- dress buses to an external device. when the external device requires access to the bus, it asserts the bus request ( br ) signal. the ( br ) signal is arbitrated with core and peripheral requests. external bus requests have the lowest priority. if no other internal request is pending, the external bus request will be granted. table 6. select boot mode (opmode, bmode1, and bmode0) opmode bmode1 bmode0 function 0 0 0 execute from external memory 16 bits (no boot) 0 0 1 boot from eprom 0 1 0 boot from host 0 1 1 reserved 1 0 0 execute from external memory 8 bits (no boot) 1 0 1 boot from uart 1 1 0 boot from spi, up to 4k bits 1 1 1 boot from spi, >4k bits up to 512k bits
?13? rev. a adsp-2191m because of synchronizer and arbi tration delays, bus grants will be provided with a minimum of three peripheral clock delays. adsp-2191m dsps will respond to the bus grant by: ? three-stating the data an d address buses and the ms3C0 , bms , ioms , rd , and wr output drivers. ? asserting the bus grant ( bg ) signal. the adsp-2191m will halt program execution if the bus is granted to an external device and an instruction fetch or data read/write request is made to external general-purpose or periph- eral memory spaces. if an instruction requires two external memory read accesses, bus requests will not be granted between the two accesses. if an instruction requires an external memory read and an external memory write access, the bus may be granted between the two accesses. the external memory interface can be configured so that the core will have exclusive use of the interface. dma and bus requests will be granted. when the external device releases br , the dsp releases bg and continues program execution from the point at which it stopped. the bus request feature operates at all times, even while the dsp is booting and reset is active. the adsp-2191m asserts the bgh pin when it is ready to start another external port access, but is held off because the bus was previously granted. this mechan ism can be extended to define more complex arbitration protocols for implementing more elaborate multimaster systems. instruction set description the adsp-2191m assembly language instruction set has an algebraic syntax that was designed for ease of coding and read- ability. the assembly language, wh ich takes full advantage of the processor?s unique architecture, offers the following benefits: ? adsp-219x assembly language sy ntax is a superset of and source-code-compatible (except for two data registers and dag base address registers) with adsp-218x family syntax. it may be necessary to restructure adsp-218x programs to accommodate the adsp-2191m?s unified memory space and to conform to its interrupt vector map. ? the algebraic syntax eliminates the need to remember cryptic assembler mnemonics. for example, a typical arithmetic add instruction, such as ar = ax0 + ay0, resembles a simple equation. ? every instruction, but two, assembles into a single, 24-bit word that can execute in a si ngle instruction cycle. the exceptions are two dual word instructions. one writes 16- or 24-bit immediate data to memory, and the other is an absolute jump/call with the 24- bit address specified in the instruction. ? multifunction instructions allo w parallel execution of an arithmetic, mac, or shift instruction with up to two fetches or one write to processor memory space during a single instruction cycle. ? program flow instructions support a wider variety of con- ditional and unconditional jumps/calls and a larger set of conditions on which to base execution of conditional instructions. development tools the adsp-2191m is supported with a complete set of software and hardware development tools, including analog devices emulators and visualdsp++ ? development environment. the same emulator hardware that supports other adsp-219x dsps, also fully emulates the adsp-2191m. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/lib rary builder), a linker, a loader, a cycle-accurate instruction-level simulator, a c/c++ compiler, and a c/c++ run-time library that includes dsp and mathemat- ical functions. two key points for these tools are: ? compiled adsp-219x c/c++ code efficiency?the compiler has been developed for efficient translation of c/c++ code to adsp-219x assembly. the dsp has architectural features that improve the efficiency of compiled c/c++ code. ? adsp-218x family code compatibility?the assembler has legacy features to ease the conversion of existing adsp-218x applications to the adsp-219x. debugging both c/c++ and assembly programs with the visu- aldsp++ debugger, programmers can: ? view mixed c/c++ and asse mbly code (interleaved source and object information) ? insert break points ? set conditional breakpoints on registers, memory, and stacks ? trace instruct ion execution ? perform linear or statistical profiling of program execution ? fill, dump, and graphically pl ot the contents of memory ? source level debugging ? create custom debugger windows the visualdsp++ ide lets programmers define and manage dsp software development. its dialog boxes and property pages let programmers configure and manage all of the adsp-219x development tools, including the syntax highlighting in the visu- aldsp++ editor. this capability permits: ? control how the development tools process inputs and generate outputs. ? maintain a one-to-one corr espondence with the tool?s command line switches. analog devices dsp emulators use the ieee 1149.1 jtag test access port of the adsp-2191m processor to monitor and control the target board pro cessor during emulation. the emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. nonin- trusive in-circuit emulation is assu red by the use of the processor?s jtag interface?the emulator does not affect target system loading or timing.
adsp-2191m ?14? rev. a in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the adsp-219x processor family. hardware tools include adsp-219x pc plug-in cards. third party software tools include dsp libraries, real-time operating systems, and block diagram design tools. designing an emulator-compatible dsp board (target) the white mountain dsp (product line of analog devices, inc.) family of emulators are tools that every dsp developer needs to test and debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. the em ulator uses the tap to access the internal features of the dsp, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the dsp must be halted to send data and commands, but once an operatio n has been completed by the emulator, the dsp system is set running at full speed with no impact on system timing. to use these emulators, the target?s design must include the interface between an analog devices jtag dsp and the emulation header on a custom dsp target board. target board header the emulator interface to an analog devices jtag dsp is a 14-pin header, as shown in figure 4 . the customer must supply this header on the target board in order to communicate with the emulator. the interface consists of a standard dual row 0.025" square post header, set on 0.1" 0.1" spacing, with a minimum post length of 0.235". pin 3 is the key position used to prevent the pod from being inserted backwards. this pin must be clipped on the target board. also, the clearance (length, width, and height) around the header must be considered. leave a cleara nce of at least 0.15" and 0.10" around the length and width of the header, and reserve a height clearance to attach and detach the pod connector. as can be seen in figure 4 , there are two sets of signals on the header. there are the standard jtag signals tms, tck, tdi, tdo, trst , and emu used for emulation purposes (via an emulator). there are also secondary jtag signals btms, btck, btdi, and btrst that are optionally used for board-level (boundary scan) testing. when the emulator is not connected to this header, place jumpers across btms, btck, btrst , and btdi as shown in figure 5 . this holds the jtag signals in th e correct state to allow the dsp to run free. remove all the jumpers when connecting the emulator to the jtag header. jtag emulator pod connector figure 6 details the dimensions of the jtag pod connector at the 14-pin target end. figure 7 displays the keep-out area for a target board header. the keep-out area allows the pod connector to properly seat onto the target board header. this board area should contain no components (chips, resistors, capacitors, etc.). the dimensions are referenced to the center of the 0.25" square post pin. figure 4. jtag target board connector for jtag equipped analog devices dsp (jumpers in place) top view 13 14 11 12 910 78 56 34 12 emu gd tms tc trst tdi tdo gd e (o pi) btms btc btrst btdi gd figure 5. jtag target boar d connector with no local boundary scan figure 6. jtag pod connector dimensions top view 13 14 11 12 910 78 56 34 12 emu gd tms tc trst tdi tdo gd e (o pi) btms btc btrst btdi gd 0 0 02
?15? rev. a adsp-2191m design-for-emulation circuit information for details on target board design issues including: single processor connections, multiproce ssor scan chains, signal buff- ering, signal termination, a nd emulator pod logic, see the ee-68: analog devices j tag emulation technical reference on the analog devices website (www.analog. com)?use site search on ?ee-68.? this document is upda ted regularly to keep pace with improvements to emulator support. additional information this data sheet provides a general overview of the adsp-2191m architecture and functionality. for detailed information on the core architecture of the adsp-219x family, refer to the adsp-219x/adsp-2191 dsp hardware reference . for details on the instruction set, refer to the adsp-219x instruction set reference . pin function descriptions adsp-2191m pin definitions are listed in table 7 . all adsp-2191m inputs are asynchronous and can be asserted asynchronously to clkin (or to tck for trst ). tie or pull unused inputs to v ddext or gnd, except for addr21?0, data15?0, pf7-0, and inputs that have internal pull-up or pull-down resistors ( trst , bmode0, bmode1, opmode, bypass, tck, tms, tdi, and reset )?these pins can be left floating. these pi ns have a logic-level hold circuit that prevents input from floating internally. the following symbols appear in the type column of table 7 : g = ground, i = input, o = output, p = power supply, and t = three-state. figure 7. jtag pod connector keep-out area 0.10" 0.1 5" table 7. pin function descriptions pin type function a21?0 o/t external port address bus d7?0 i/o/t external port data bus, least significant 8 bits d15 /pf15 /spi1sel7 i/o/t i/o i data 15 (if 16-bit external bus)/programmable flags 15 (if 8-bit external bus)/spi1 slave select output 7 (if 8-bit exte rnal bus, when spi1 enabled) d14 /pf14 /spi0sel7 i/o/t i/o i data 14 (if 16-bit external bus)/programmable flags 14 (if 8-bit external bus)/spi0 slave select output 7 (if 8-bit exte rnal bus, when spi0 enabled) d13 /pf12 /spi1sel6 i/o/t i/o i data 13 (if 16-bit external bus)/programmable flags 13 (if 8-bit external bus)/spi1 slave select output 6 (if 8-bit exte rnal bus, when spi1 enabled) d12 /pf12 /spi0sel6 i/o/t i/o i data 12 (if 16-bit external bus)/programmable flags 12 (if 8-bit external bus)/spi0 slave select output 6 (if 8-bit exte rnal bus, when spi0 enabled) d11 /pf11 /spi1sel5 i/o/t i/o i data 11 (if 16-bit external bus)/programmable flags 11 (if 8-bit external bus)/spi1 slave select output 5 (if 8-bit exte rnal bus, when spi1 enabled) d10 /pf10 /spi0sel5 i/o/t i/o i data 10 (if 16-bit external bus)/programmable flags 10 (if 8-bit external bus)/spi0 slave select output 5 (if 8-bit exte rnal bus, when spi0 enabled) d9 /pf9 /spi1sel4 i/o/t i/o i data 9 (if 16-bit external bus) /programmable flags 9 (if 8-bit ex ternal bus)/spi1 slave select output 4 (if 8-bit external bus, when spi1 enabled) d8 /pf8 /spi0sel4 i/o/t i/o i data 8 (if 16-bit external bus) /programmable flags 8 (if 8-bit ex ternal bus)/spi0 slave select output 4 (if 8-bit external bus, when spi0 enabled) pf7 /spi1sel3 /df i/o/t i i programmable flags 7/spi1 slave select outp ut 3 (when spi0 enabled)/divisor frequency (divisor select for pll input during boot) pf6 /spi0sel3 /msel6 i/o/t i i programmable flags 6/spi0 slave select output 3 (when spi0 enabled)/multiplier select 6 (during boot)
adsp-2191m ?16? rev. a pf5 /spi1sel2 /msel5 i/o/t i i programmable flags 5/spi1 slave select output 2 (when spi0 enabled)/multiplier select 5 (during boot) pf4 /spi0sel2 /msel4 i/o/t i i programmable flags 4/spi0 slave select output 2 (when spi0 enabled)/multiplier select 4 (during boot) pf3 /spi1sel1 /msel3 i/o/t i i programmable flags 3/spi1 slave select output 1 (when spi0 enabled)/multiplier select 3 (during boot) pf2 /spi0sel1 /msel2 i/o/t i i programmable flags 2/spi0 slave select output 1 (when spi0 enabled)/multiplier select 2 (during boot) pf1 /spiss1 /msel1 i/o/t i i programmable flags 1/spi1 slave select inpu t (when spi1 enabled)/multiplier select 1 (during boot) pf0 /spiss0 /msel0 i/o/t i i programmable flags 0/spi0 slave select inpu t (when spi0 enabled)/multiplier select 0 (during boot) rd o/t external port read strobe wr o/t external port write strobe ack i external port access ready acknowledge bms o/t external port boot space select ioms o/t external port io space select ms3C0 o/t external port memory space selects br i external port bus request bg oexternal port bus grant bgh o external port bus grant hang had15?0 i/o/t host port multip lexed address and data bus ha16 i host port msb of address bus hack_p i host port ack polarity hrd i host port read strobe hwr i host port write strobe hack o host port access ready acknowledge hale i host port address latch st robe or addres s cycle control hcms i host port internal memory?internal i/o memory?boot memory select hcioms i host port internal i/o memory select clkin i clock input/ oscillator input xtal o oscillator output bmode1?0 i boot mode 1?0. the bmod e1 and bmode0 pins have 85 k ? internal pull-up resistors. opmode i operating mode. the opmode pin has a 85 k ? internal pull-up resistor. clkout o clock output bypass i phase-lock-loop (pll) bypass mode. the bypass pin has a 85 k ? internal pull-up resistor. rclk1?0 i/o/t sport1?0 receive clock rclk2/sck1 i/o/t sport2 receive clock/spi1 serial clock rfs1?0 i/o/t sport1?0 receive frame sync rfs2/mosi1 i/o/t sport2 receive frame sync /spi1 master-output, slave-input data tclk1?0 i/o/t sport1?0 transmit clock tclk2/sck0 i/o/t sport2 transmit clock/spi0 serial clock tfs1?0 i/o/t sport1?0 transmit frame sync tfs2/mosi0 i/o/t sport2 transmit frame sy nc/spi0 master-output, slave-input data dr1?0 i/t sport1?0 serial data receive dr2/miso1 i/o/t sport2 serial data recei ve/spi1 master-input, slave-output data dt1?0 o/t sport1?0 serial data transmit dt2/miso0 i/o/t sport2 serial data transm it/spi0 master-input, slave-output data table 7. pin function descriptions (continued) pin type function
?17? rev. a adsp-2191m tmr2?0 i/o/t timer output or capture rxd i uart serial receive data txd o uart serial transmit data reset i processor reset. resets the adsp-2191m to a known state and begi ns execution at the program memory location specified by th e hardware reset vector address. the reset input must be asserted (low) at powerup. the reset pin has an 85 k ? internal pull-up resistor. tck i test clock (jtag). provides a clock for jtag boundary scan. the tck pin has an 85 k ? internal pull-up resistor. tms i test mode select (jtag). us ed to control the test state ma chine. the tms pin has an 85 k ? internal pull-up resistor. tdi i test data input (jtag). provides serial data for the boundary scan logic. the tdi pin has a 85 k ? internal pull-up resistor. tdo o test data output (jtag). serial scan output of the boundary scan path. trst i test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after powerup or held low for proper operation of the adsp-2191m. the trst pin has a 65 k ? internal pull-down resistor. emu o emulation status (jtag). mu st be connected to the adsp -2191m emulator target board connector only. v ddint p core power supply. nominally 2.5 v dc and supplies the dsp?s core processor. (four pins) v ddext p i/o power supply. nominally 3.3 v dc. (nine pins) gnd g power supply return. (twelve pins) nc do not connect. reserved pins that must be left open and unconnected. table 7. pin function descriptions (continued) pin type function
adsp-2191m ?18? rev. a specifications recommended operating conditions parameter test conditions k grade (commercial) min max b grade (industrial) min max unit v ddint internal (core) supply vo l t a g e 2.37 2.63 2.37 2.63 v v ddext external (i/o) supply vo l t a g e 2.97 3.6 2.97 3.6 v v ih high level input voltage @ v ddint = max, v ddext = max 2.0 v ddext +0.3 2.0 v ddext +0.3 v v il low level input voltage @ v ddint = min, v ddext = min ?0.3 +0.8 ?0.3 +0.8 v t amb ambient operating te m p e r a t u r e 070 ?40+85 oc specifications subject to change without notice. electrical characteristics k and b grades parameter test conditions min typ max unit v oh high level output voltage 1 1 applies to output and bidirectional pins: data15?0, ad dr21?0, had15?0, ms3C0 , ioms , rd , wr , clkout, hack, pf7?0, tmr2?0, bgh , bg , dt0, dt1, dt2/miso0, tclk0, tclk1, tclk2/sck0, rclk0, rclk1, rclk2/sck1, tfs0, tfs1, tfs2/mosi0, rfs0, rfs1, rfs2/mosi1, bms , tdo, txd, emu , dr2/miso1. @ v ddext = min, i oh = ?0.5 ma 2.4 v v ol low level output voltage 1 @ v ddext = min, i ol = 2.0 ma 0.4 v i ih high level input current 2, 3 2 applies to input pins: ack, br , hcms , hcioms , ha16, hale, hrd , hwr , clkin, dr0, dr1, rxd, hack_p. 3 applies to input pins with internal pull-ups: bm ode0, bmode1, opmode, bypass, tck, tms, tdi, reset . @ v ddext = max, v in = v dd max 10 a i il low level input current 3, 4 4 applies to input pin with internal pull-down: trst. @ v ddext = max, v in = 0 v 10 a i ihp high level input current 5 @ v ddext = max, v in = v dd max 30 100 a i ilp low level input current 4 @ v ddext = max, v in = 0 v 20 70 a i ozh three-state leakage current 5 5 applies to three-statable pins: data15?0, addr21?0, ms3C0 , rd , wr , pf7?0, bms , ioms , tfsx, rfsx, tdo, emu , tclkx, rclkx, dtx, had15?0, tmr2?0. @ v ddext = max, v in = v dd max 10 a i ozl three-state leakage current 6 @ v ddext = max, v in = 0 v 10 a c in input capacitance 6, 7 6 applies to all signal pins. 7 guaranteed, but not tested. f in = 1 mhz, t case = 25c, v in = 2.5 v 8pf specifications subject to change without notice.
?19? rev. a adsp-2191m absolute maximum ratings esd sensitivity power dissipation using the operation-versus-current information in table 8 , designers can estimate the adsp-2191m?s internal power supply (v ddint ) input current for a specific applicatio n, according to the formula for i ddint calculation beneath table 8 . for calculation of external supply current and total supply current, see power dissipation on page 40. v ddint internal (core) supply voltage 1 . . . ?0.3 v to +3.0 v 1 stresses greater than those listed ab ove may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v ddext external (i/o) supply voltage . . . . ?0.3 v to +4.6 v v il ?v ih input voltage . . . . . . . . . . ?0.5 v to v ddext +0.5 v v ol ?v oh output voltage swing. . . ?0.5 v to v ddext +0.5 v t store storage temperature range . . . . . .?65oc to +150oc t lead lead temperature of st-144 (5 seconds) . . . . 185oc caution esd (electrostatic discharge) sensitive device. electrostat ic charges as high as 4000 v readily accumulate on the hu man body and test equipment and can discharge without detection. although the ad sp-2191m features propriet ary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precaut ions are recommended to avoid perfor- mance degradation or loss of functionality. table 8. operation types versus input current k-grade i ddint (ma) cclk = 160 mhz b-grade i ddint (ma) 1 cclk = 140 mhz core peripheral core peripheral activity typ 1 1 test conditions: v ddint = 2.50 v; hclk (peripheral clock) freq uency = cclk/2 (core clock/2) frequency; t amb = 25oc. max 2 2 test conditions: v ddint = 2.65 v; hclk (peripheral clock) freq uency = cclk/2 (core clock/2) frequency; t amb = 25oc. ty p 1 max 2 ty p 1 max 2 ty p 1 max 2 power down 3 3 pll, core, peripheral clocks, and clkin are disabled. 100 a 600 a 0 50 a 100 a 500 a 0 50 a idle 1 4 4 pll is enabled and core and peripheral clocks are disabled. 12581247 idle 2 5 5 core clk is disabled and peripheral clock is enabled. 126070125562 ty pi c al 6 6 all instructions execute from internal memory. 50% of the instructio ns are repeat macs with dual operand addressing, with chang ing data fetched using a linear address sequence. 50% of the instructions are type 3 instructions. 184 210 60 70 165 185 55 62 peak 7 7 all instructions execute from internal memory. 100% of the instr uctions are macs with dual operand addressing, with changing da ta fetched using a linear address sequence. 215 240 60 70 195 210 55 62 i ddint %typical i ddint-typical () = %idle i ddint-idle () %power down i ddint-pwrdwn () ++
adsp-2191m ?20? rev. a timing specifications this section contains timing in formation for the dsp?s external signals. use the exact information given. do not attempt to derive parameters from the addition or subtraction of other information. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, parameters cannot be added meaningfully to derive longer times. switching characteristics specify how the processor changes its signals. no control is possible over this timing; circuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics indicate what the processor will do in a given circumstance. switching character- istics can also be used to ensure that any timing requirement of a device connected to the processo r (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processo r, such as the data input for a read operation.timing requirements guarantee that the processor operates correctly with other devices. clock in and clock out cycle timing table 9 and figure 8 describe clock and reset operations. com- binations of clkin and clock multipliers must not select core/peripheral clocks in excess of 160/80 mhz for commercial grade and 140/70 mhz for industrial grade, when the peripheral clock rate is one-half the core cl ock rate. if the peripheral clock rate is equal to the core clock rate, the maximum peripheral clock rate is 80 mhz for both commerc ial and industrial grade parts. the peripheral clock is supp lied to the clkout pins. when changing from bypass mode to pll mode, allow 512 hclk cycles for the pll to stabilize. table 9. clock in and clock out cycle timing parameter min max unit switching characteristics t ckod clkout delay from clkin 0 5.8 ns t cko clkout period 1 12.5 ns timing requirements t ck clkin period 2, 3 10 200 ns t ckl clkin low pulse 4.5 ns t ckh clkin high pulse 4.5 ns t wrst reset asserted pulsewidth low 200t clkout ns t mss mselx/bypass stable before reset deasserted setup 40 s t msh mselx/bypass stable after reset deasserted hold 1000 ns t msd mselx/bypass stable after reset asserted 200 ns t pfd flag output disable time after reset asserted 10 ns 1 clkout jitter can be as great as 8 ns wh en clkout frequency is less than 20 mhz. for fr equencies greater than 20 mhz, jitter is less than 1 ns. 2 in clock multiplier mode and msel6?0 set for 1:1 (or clkin = cclk), t ck = t cclk . 3 in bypass mode, t ck = t cclk . figure 8. clock in and clock out cycle timing t ckod clkout msel6?0 bypass df reset cli wrst cdd c cl msh co pd msd mss
?21? rev. a adsp-2191m programmable flags cycle timing table 10 and figure 9 describe programmable flag operations. timer pwm_out cycle timing table 11 and figure 10 describe timer expired operations. the input signal is asynchronous in ?width capture mode? and has an absolute maximum input frequency of 40 mhz. table 10. programmable flags cycle timing parameter min max unit switching characteristics t dfo flag output delay with respect to clkout 7 ns t hfo flag output hold after clkout high 6 ns timing requirement t hfi flag input hold is asynchronous 3 ns figure 9. programmable flags cycle timing pf (input) t hfi pf (output) clkout flag input t dfo t hfo flag output table 11. timer pwm_out cycle timing parameter min max unit switching characteristic t hto timer pulsewidth output 1 12.5 (2 32 ?1) cycles ns 1 the minimum time for t hto is one cycle, and the maximum time for t hto equals (2 32 ?1) cycles. figure 10. timer pwm_out cycle timing hclk pwm_out t hto
adsp-2191m ?22? rev. a external port write cycle timing table 12 and figure 11 describe external port write operations. the external port lets systems exte nd read/write accesses in three ways: waitstates, ack input, and combined waitstates and ack. to add waits with ack, the dsp must see ack low at the rising edge of emi clock. ack low causes the dsp to wait, and the dsp requires two emi clock cycles after ack goes high to finish the access. for more information, see the external port chapter in the adsp-219x/adsp-2191 dsp hardware reference . table 12. external port write cycle timing parameter 1, 2 min max unit switching characteristics t csws chip select asserted to wr asserted delay 0.5t hclk ?4 ns t aws address valid to wr setup and delay 0.5t hclk ?3 ns t wscs wr deasserted to chip select deasserted 0.5t hclk ?4 ns t wsa wr deasserted to address invalid 0.5t hclk ?3 ns t ww wr strobe pulsewidth t hclk ?2+w 3 ns t cda wr to data enable access delay 0ns t cdd wr to data disable access delay 0.5t hclk ?3 0.5t hclk +4 ns t dsw data valid to wr deasserted setup t hclk +1+w 3 t hclk +7+w 3 ns t dhw wr deasserted to data invalid hold time; e_whc 4 3.4 ns t dhw wr deasserted to data invalid hold time; e_whc 4 t hclk +3.4 ns t wwr wr deasserted to wr , rd asserted t hclk timing requirements t akw ack strobe pulsewidth 12.5 ns t dwsak ack delay from wr low 0 ns 1 t hclk is the peripheral clock period. 2 these are timing parameters that are based on worst-case operating conditions. 3 w = (number of waitstates specified in wait register) t hclk. 4 write hold cycle?memory select control registers (ms ctl). figure 11. external po rt write cycle timing d15?0 t aws t ww t akw t dhw t cdd ack wr 210 ms3C0 iom s bms csws ws wscs cd dws rd dsw wwr
?23? rev. a adsp-2191m external port read cycle timing table 13 and figure 12 describe external port read operations. for additional information on the ack signal, see the discussion on page 22 . table 13. external port read cycle timing parameter 1, 2 min max unit switching characteristics t csrs chip select asserted to rd asserted delay 0.5t hclk ?3 ns t ars address valid to rd setup and delay 0.5t hclk ?3 ns t rscs rd deasserted to chip sel ect deasserted setup 0.5t hclk ?2 ns t rw rd strobe pulsewidth t hclk ?2+w 3 ns t rsa rd deasserted to addr ess invalid setup 0.5t hclk ?2 ns t rwr rd deasserted to wr , rd asserted t hclk timing requirements t akw ack strobe pulsewidth t hclk ns t rda rd asserted to data access setup t hclk ?4+w 3 ns t ada address valid to data access setup t hclk +w 3 ns t sda chip select asserted to data access setup t hclk +w 3 ns t sd data valid to rd deasserted setup 7 ns t hrd rd deasserted to data invalid hold 0 ns t drsak ack delay from rd low 0 ns 1 t hclk is the peripheral clock period. 2 these are timing parameters that are based on worst-case operating conditions. 3 w = (number of waitstates specified in wait register) t hclk . figure 12. external po rt read cycle timing d15?0 t ars t rw t akw t cda t rda t ada t sda t sd t hrd ack rd 210 csrs rs rscs drs rwr ms30 ioms bms wr
adsp-2191m ?24? rev. a external port bus request and grant cycle timing table 14 and figure 13 describe external port bus request and bus grant operations. table 14. external port bus request and grant cycle timing parameter 1, 2 min max unit switching characteristics t sd clkout high to xms , address, and rd / wr disable 0.5t hclk +1 ns t se clkout low to xms , address, and rd / wr enable04ns t dbg clkout high to bg asserted setup 0 4 ns t ebg clkout high to bg deasserted hold time 0 4 ns t dbh clkout high to bgh asserted setup 0 4 ns t ebh clkout high to bgh deasserted hold time04ns timing requirements t bs br asserted to clkout high setup 4.6 ns t bh clkout high to br deasserted hold time 0 ns 1 t hclk is the peripheral clock period. 2 these are timing parameters that are based on worst-case operating conditions. figure 13. external port bus request and grant cycle timing t bh a21?0 clkout t bs t sd t sd t sd t dbg t dbh t se t se t se t ebg t ebh bgh wr rd ms30 ioms bms br bg
?25? rev. a adsp-2191m host port ale mode write cycle timing table 15 and figure 14 describe host port write operations in address latch enable (ale) mode. for more information on ack, ready, ale, and acc mode selection, see the host port modes description on page 8 . table 15. host port ale mode write cycle timing parameter min max unit switching characteristics t whks1 hwr asserted to hack assert ed (setup, ack mode) first byte 10 5t hclk +t nh 1 ns t whks2 hwr asserted to hack asserted (setup, ack mode) 2 10 ns t whkh hwr deasserted to hack deas serted (hold, ack mode) 10 ns t whs hwr asserted to hack asserted (setup, ready mode) 10 ns t whh hwr asserted to hack deasserted (hold, ready mode) first byte 05t hclk +t nh 1 ns timing requirements t csal hcms or hcioms asserted to hale asserted 0ns t alpw hale asserted pulsewidth 4 ns t alcsw hale deasserted to hcms or hcioms deasserted 1 ns t wcsw hwr deasserted to hcms or hcioms deasserted 0 ns t alw hale deasserted to hwr asserted 1 ns t wcs hwr deasserted (after last byte) to hcms or hcioms deasserted (ready for next write) 0ns t hkwd hack asserted to hwr deasserted (hold, ack mode) 1.5 ns t aals address valid to hale deasserted (setup) 2 ns t alah hale deasserted to address invalid (hold) 4 ns t dws data valid to hwr deasserted (setup) 4 ns t wdh hwr deasserted to data invalid (hold) 1 ns 1 t nh are peripheral bus latencies (n t hclk ); these are internal dsp latencies related to the number of peripheral dmas attempting to access dsp memory at the same time. 2 measurement is for the second, third, or fourth byte of a host write transaction. the quantity of bytes to complete a host writ e transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
adsp-2191m ?26? rev. a figure 14. host port al e mode write cycle timing address valid address valid t alah data valid data valid last by t e fi rs t by t e start next word start first word t wdh t aa l s t dws t whks t wh kh hack each byte hack first byte t alpw t alcsw t alw t hkw d t wcsw t whs t whh had15? 0 ha16 hale hack (ready mode) t cs a l t wcs hack (ack mode) hwr hcms hioms
?27? rev. a adsp-2191m host port acc mode write cycle timing table 16 and figure 15 describe host port write operations in address cycle control (acc) mode. for more information on ack, ready, ale, and acc mode selection, see the host port modes description on page 8 . table 16. host port acc mode write cycle timing parameter min max unit switching characteristics t whks1 hwr asserted to hack asserted (ack mode) first byte 10 5t hclk +t nh 1 ns t whks2 hwr asserted to hack asserted (setup, ack mode) 2 12 ns t whkh hwr deasserted to hack deas serted (hold, ack mode) 10 ns t whs hwr asserted to hack asserted (setup, ready mode) 10 ns t whh hwr asserted to hack deasserted (hold, ready mode) first byte 05t hclk +t nh 1 ns t wshks hwr asserted to hack asserted (setup) during address latch 10 ns t whhkh hwr deasserted to hack deasserted (hold) during address latch 10 ns timing requirements t wal hwr asserted to hale deasserted (delay) 1.5 ns t csal hcms or hcioms asserted to hale asserted (delay) 0ns t alcs hale deasserted to optional hcms or hcioms deasserted 1ns t wcsw hwr deasserted to hcms or hcioms deasserted 0 ns t alw hale asserted to hwr asserted 0.5 ns t csw hcms or hcioms asserted to hwr asserted 0ns t wcs hwr deasserted (after last byte) to hcms or hcioms deasserted (ready for next write) 0ns t alew hale deasserted to hwr asserted 1 ns t hkwd hack asserted to hwr deasserted (hold, ack mode) 1.5 ns t adw address valid to hwr asserted (setup) 3 ns t wad hwr deasserted to addr ess invalid (hold) 3 ns t dws data valid to hwr deasserted (setup) 2 ns t wdh hwr deasserted to data invalid (hold) 2 ns t hkwal hack asserted to hwr deasserted (hold) during address latch 2 2ns 1 t nh are peripheral bus latencies (n t hclk ); these are internal dsp latencies related to the numb er of peripheral dmas attempting to access dsp memory at the same time. 2 measurement is for the second, third, or fourth byte of a host write transaction. the quantity of bytes to complete a host wri te transaction is dependent on the data bus size (8 or 16 bits ) and the data type (16 or 24 bits).
adsp-2191m ?28? rev. a figure 15. host port a cc mode write cycle timing t dws t adw address valid data valid data valid address valid hack first byte t wdh had15?0 ha16 t wa d last byte first by t e start next word start first word t whkh t whks t csal t wcs hale t al e w t hkwd hack each byt e hack (ready mo de ) t wal t al cs t alw t csw t wcsw t whs t whh t whhkh t ws hks t hkw al ha c k (a c k mo d e) hwr hcms hioms
?29? rev. a adsp-2191m host port ale mode read cycle timing table 17 and figure 16 describe host port read operations in address latch enable (ale) mode. for more information on ack, ready, ale, and acc mode selection, see the host port modes description on page 8 . table 17. host port ale mode read cycle timing parameter min max unit switching characteristics t rhks1 hrd asserted to hack asserted (ack mode) first byte 12t hclk 15t hclk +t nh 1 ns t rhks2 hrd asserted to hack asserted (setup, ack mode) 2 12 ns t rhkh hrd deasserted to hack deasserted (hold, ack mode) 10 ns t rhs hrd asserted to hack asserted (setup, ready mode) 10 ns t rhh hrd asserted to hack deasserted (hold, ready mode) first byte 12t hclk 15t hclk +t nh 1 ns t rdh hrd deasserted to data invalid (hold) 1 ns t rdd hrd deasserted to data disable 10 ns timing requirements t csal hcms or hcioms asserted to hale asserted (delay) 0ns t alcs hale deasserted to optional hcms or hcioms deasserted 1ns t rcsw hrd deasserted to hcms or hcioms deasserted 0 ns t alr hale deasserted to hrd asserted 5 ns t rcs hrd deasserted (after last byte) to hcms or hcioms deasserted (ready for next read) 0ns t alpw hale asserted pulsewidth 4 ns t hkrd hack asserted to hrd deasserted (hold, ack mode) 1.5 ns t aals address valid to hale deasserted (setup) 2 ns t alah hale deasserted to address invalid (hold) 4 ns 1 t nh are peripheral bus latencies (n t hclk ); these are internal dsp latencies related to the number of peripherals attempting to access dsp memory at the same time. 2 measurement is for the second, third, or fourth byte of a host re ad transaction. the quantity of bytes to complete a host read transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
adsp-2191m ?30? rev. a figure 16. host port ale mode read cycle timing t aals t hkrd address valid address valid t alah data valid da t a valid last byte first byte start next w ord start fi rs t wo rd t rdh t rcs t rhkh ha ck (ready mo de ) hack for each byte t alpw t alc s t al r t rcsw hack first byte t rh s t rh h t rh k s t rdd had15?0 ha16 t csal hal e hack (ack mode) hrd hcms hioms
?31? rev. a adsp-2191m host port acc mode read cycle timing table 18 and figure 17 describe host port read operations in address cycle control (acc) mode. for more information on ack, ready, ale, and acc mode selection, see the host port modes description on page 8 . table 18. host port acc mode read cycle timing parameter min max unit switching characteristics t rhks1 hrd asserted to hack asserted (ack mode) first byte 12t hclk 15t hclk +t nh 1 ns t rhks2 hrd asserted to hack asserted (setup, ack mode) 2 10 ns t rhkh hrd deasserted to hack deasserted (hold, ack mode) 10 ns t rhs hrd asserted to hack asserted (setup, ready mode) 10 ns t rhh hrd asserted to hack deasserted (hold, ready mode) first byte 12t hclk 15t hclk +t nh 1 ns t rdh hrd deasserted to data invalid (hold) 1 ns t wshks hwr asserted to hack asserted (setup) during address latch 10 ns t whhkh hwr deasserted to hack deasserted (hold) during address latch 10 ns t rdd hrd deasserted to data disable 10 ns timing requirements t csal hcms or hcioms asserted to hale asserted (delay) 0ns t alcs hale deasserted to optional hcms or hcioms deasserted 1ns t rcsw hrd deasserted to hcms or hcioms deasserted 0 ns t alw hale asserted to hwr asserted 0.5 ns t aler hale deasserted to hwr asserted 1 ns t csr hcms or hcioms asserted to hrd asserted 0ns t rcs hrd deasserted (after last byte) to hcms or hcioms deasserted (ready for next read) 0ns t wal hwr deasserted to hale deasserted (delay) 2.5 ns t hkrd hack asserted to hrd deasserted (hold, ack mode) 1.5 ns t adw address valid to hwr deasserted (setup) 2 ns t wad hwr deasserted to addr ess invalid (hold) 1 ns t hkwal hack asserted to hwr deasserted (hold) during address latch 2 2ns 1 t nh are peripheral bus latencies (n t hclk ); these are internal dsp latencies related to the number of peripherals attempting to access dsp memory at the same time. 2 measurement is for the second, third, or fourth byte of a host read transaction. the quantity of bytes to complete a host read transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
adsp-2191m ?32? rev. a figure 17. host port acc mode read cycle timing address valid data valid data valid address valid t rdh h ad15? 0 ha16 t adw last b y te first b y te start ne xt w or d start fi rs t w ord t rhkh t hkrd t csal t rhks tt rcs ha l e t alw hack (a c k mode) hack each byte t al c s t csr t al e r t rc s w hack (ready mode) hack first byte t rhs t rhh t wshks t whhkh t hk w al t rdd t wal t wad hwr hrd hcms hioms
?33? rev. a adsp-2191m serial ports table 19 and figure 18 describe sport transmit and receive operations, while figure 19 and figure 20 describe sport frame sync operations. table 19. serial ports 1, 2 parameter min max unit external clock timing requirements t sfse tfs/rfs setup before tclk/rclk 3 4ns t hfse tfs/rfs hold after tclk/rclk 3 4ns t sdre receive data setup before rclk 3 1.5 ns t hdre receive data hold after rclk 3 4ns t sclkw tclk/rclk width 0.5t hclk ?1 ns t sclk tclk/rclk period 2t hclk ns internal clock timing requirements t sfsi tfs setup before tclk 4 ; rfs setup before rclk 3 4ns t hfsi tfs/rfs hold after tclk/rclk 3 3ns t sdri receive data setup before rclk 3 2ns t hdri receive data hold after rclk 3 5ns external or internal cloc k switching characteristics t dfse tfs/rfs delay after tclk/rclk (internally generated fs) 4 14 ns t hofse tfs/rfs hold after tclk/rclk (internally generated fs) 4 3ns external clock switching characteristics t ddte transmit data delay after tclk 4 13.4 ns t hdte transmit data hold after tclk 4 4ns internal clock switching characteristics t ddti transmit data delay after tclk 4 13.4 ns t hdti transmit data hold after tclk 4 4ns t sclkiw tclk/rclk width 0.5t hclk ?3.5 0.5t hclk +2.5 ns enable and three-state 5 switching characteristics t dtene data enable from external tclk 4 012.1ns t ddtte data disable from external tclk 4 13 ns t dteni data enable from internal tclk 4 013ns t ddtti data disable from external tclk 4 12 ns external late frame sync switching characteristics t ddtlfse data delay from late external tfs with mce=1, mfd=0 6, 7 10.5 ns t dtenlfse data enable from late fs or mce = 1, mfd = 0 6, 7 3.5 ns 1 to determine whether communication is possible between two devices at clock speed n, the following specifications must be confi rmed: 1) frame sync delay and frame sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) sclk width. 2 word selected timing for i 2 s mode is the same as tfs/rfs timing (normal framing only). 3 referenced to sample edge. 4 referenced to drive edge. 5 only applies to sport0/1. 6 mce=1, tfs enable, and tfs valid follow t ddtenfs and t ddtlfse . 7 if external rfsd/tfs s etup to rclk/tclk>0.5t lsck , t ddtlsck and t dtenlsck apply; otherwise t ddtlfse and t dtenlfs apply.
adsp-2191m ?34? rev. a figure 18. serial ports dt dt t ddtte t ddten t ddtti t ddtin drive edge drive edge drive edge drive edge tclk/rclk tclk/rclk tclk (ext) tfs (?late,? ext.) t sdri rclk rfs dr drive edge sample edge t hdri t sfsi t hfsi t dfse t hofse t sclkiw data receive-internal clock t sdre data receive-external clock rclk rfs dr drive edge sample edge t hdre t sfse t hfse t dfse t sclkw t hofse note: either the rising edge or falling edge of rclk or tclk can be used as the active sampling edge. t ddti t hdti tclk tfs dt drive edge sample edge t sfsi t hfsi t sclkiw t dfse t hofse data transmit-internal clock t ddte t hdte tclk tfs dt drive edge sample edge t sfse t hfse t dfse t sclkw t hofse data transmit-external clock note: either the rising edge or falling edge of rclk or tclk can be used as the active sampling edge. tclk (int) tfs (?late,? int.)
?35? rev. a adsp-2191m figure 19. serial ports? external late frame sync (frame sync setup > 0.5t sclk ) figure 20. serial ports?external late frame sync (frame sync setup < 0.5t hclk ) drive sample drive t dtenlfse t ddtlfse external rfs with mce = 1, mfd = 0 1st bit 2nd bit dt rclk rfs late external tfs t hdte/i t ddte/ i t sfse /i drive sample drive t dtenlfse t ddtlfse 1st bit 2nd bit dt tclk tfs t hdte/ i t ddte/i t hosfse/ i t hosfse/ i t sfse/i t ddtlfse drive sample drive t dtenlfse t ddtlfse external rfs with mce = 1, mfd = 0 1st bit 2nd bit dt rclk rfs late external tfs t hdte/ i t ddte/i t sfse/ i drive sample drive t dtenlfse 1st bit 2nd bit dt tclk tfs t hdte/ i t ddte/ i t hofse/i t hofse/ i t sfse/i
adsp-2191m ?36? rev. a serial peripheral interfac e (spi) port?master timing table 20 and figure 21 describe spi port master operations. table 20. serial peripheral interface (spi) port?master timing parameter min max unit switching characteristics t sdscim spixsel low to first sclk edge (x=0 or 1) 2t hclk ?3 ns t spichm serial clock high period 2t hclk ?3 ns t spiclm serial clock low period 2t hclk ?3 ns t spiclk serial clock period 4t hclk ?1 ns t hdsm last sclk edge to spixsel high (x = 0 or 1) 2t hclk ?3 ns t spitdm sequential transfer delay 2t hclk ?2 ns t ddspid sclk edge to data output valid (data out delay) 0 6 ns t hdspid sclk edge to data output invalid (data out hold) 0 5 ns timing requirements t sspid data input valid to sclk edge (data input setup) 8 ns t hspid sclk sampling edge to data input invalid (data in hold) 1 ns figure 21. serial peripheral interface (spi) port?master timing t hspid t hdspid lsb msb t hspid t ddspid mosi (output) miso (input) spixsel (output) (x 0 1) scl (cpol 0) (output) scl (cpol 1) (output) spichm spiclm spiclm spicl spichm hdsm spitdm hdspid lsb lid lsb msb msb lid hspid ddspid mosi (output) miso (iput) sspid cph 0 msb lid sdscim sspid lsb lid cph 1 sspid
?37? rev. a adsp-2191m serial peripheral interface (spi) port?slave timing table 21 and figure 22 describe spi port slave operations. table 21. serial peripheral interface (spi) port?slave timing parameter min max unit switching characteristics t dsoe spiss assertion to data out active 08ns t dsdhi spiss deassertion to data high impedance 010ns t ddspid sclk edge to data out valid (data out delay) 0 10 ns t hdspid sclk edge to data out invalid (data out hold) 0 10 ns timing requirements t spichs serial clock high period 2t hclk ns t spicls serial clock low period 2t hclk ns t spiclk serial clock period 4t hclk ns t hds last spiclk edge to spiss not asserted 2t hclk ns t spitds sequential transfer delay 2t hclk +4 ns t sdsci spiss assertion to first spiclk edge 2t hclk ns t sspid data input valid to sclk edge (data input setup) 1.6 ns t hspid sclk sampling edge to data input invalid (data in hold) 2.4 ns figure 22. serial peripheral interface (spi) port?slave timing t hspid t ddspid t dsdhi lsb msb msb valid t hspid t dsoe t hdspid miso (output) mosi (input) t sspid spiss (iput) scl (cpol 0) (iput) scl (cpol 1) (iput) sdsci spichs spicls spicls spicl hds spichs sspid hspid dsdhi lsb lid msb msb lid dsoe ddspid miso (output) mosi (iput) sspid lsb lid lsb spitds cph 0 cph 1 ddspid
adsp-2191m ?38? rev. a universal asynchronous rece iver-transmitter (uart) port?receive and transmit timing figure 23 describes uart port receive and transmit operations. the maximum baud rate is hclk/16. as shown in figure 23 there is some latency between the generation internal uart interrupts and the external data operations. these latencies are negligible at the data transmission rates for the uart. figure 23. uart port?rec eive and transmit timing rxd data(5?8) internal uart receive interrupt uart receive bit set by data stop; cleared by fifo read hclk (sample clock) txd data(5?8) stop (1?2) internal uart transmit interrupt uart transmit bit set by program; cleared by write to transmit start stop transmit receive as data written to buffer
?39? rev. a adsp-2191m jtag test and emulation port timing table 22 and figure 24 describe jtag port operations. table 22. jtag port timing parameter min max unit switching characteristics t dtdo tdo delay from tck low 8 ns t dsys system outputs delay after tck low 1 022ns timing requirements t tck tck period 20 ns t stap tdi, tms setup before tck high 4 ns t htap tdi, tms hold after tck high 4 ns t ssys system inputs setu p before tck low 2 4ns t hsys system inputs hold after tck low 2 5ns t trstw trst pulsewidth 3 4t tck ns 1 system outputs = da ta15?0, addr21?0, ms3C0 , rd , wr , ack, clkout, bg , pf7?0, timexp, dt0, dt1, t clk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, bms . 2 system inputs = data15?0, addr21?0, rd , wr , ack, br , bg , pf7?0, dr0, dr1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, clkin, reset . 3 50 mhz max. figure 24. jtag port timing tms tdi tdo system inputs system outputs tck t tck t htap t stap t dtdo t ssys t hsys t dsys
adsp-2191m ?40? rev. a output drive currents figure 25 shows typical i-v characteri stics for the output drivers of the adsp-2191m. the curves represent the current drive capability of the output drivers as a function of output voltage. power dissipation total power dissipation has two co mponents, one due to internal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruction execution sequence and the data operands involved. the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: ? number of output pins that switch during each cycle (o) ? the maximum frequency at wh ich they can switch (f) ? their load capacitance (c) ? their voltage swing (v dd ) and is calculated by the formula below. the load capacitance includes the processor?s package capaci- tance (c in ). the switching frequency includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1/(2t ck ). the write strobe can switch every cycle at a frequency of 1/t ck . select pins switch at 1/(2t ck ), but selects can switch on each cycle. for example, estimate p ext with the following assumptions: ? a system with one bank of external data memory?asyn- chronous ram (16-bit) ? one 64k 16 ram chip is used with a load of 10 pf ? maximum peripheral speed cclk = 80 mhz, hclk = 80 mhz ? external data memory writes occur every other cycle, a rate of 1/(4t hclk ), with 50% of the pins switching ? the bus cycle time is 80 mhz (t hclk = 12.5 ns) the p ext equation is calculated for each class of pins that can drive as shown in table 23 . a typical power consumption can now be calculated for these conditions by adding a typical in ternal power dissipation with the following formula. where: ? p ext is from table 23 ? p int is i ddint 2.5 v, using the calculation i ddint listed in power dissipation on page 19 . note that the conditions causing a worst-case p ext are different from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pi ns are switching from all ones to all zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. test conditions the dsp is tested for output enable, disable, and hold time. output disable time output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ?v is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the equation below. figure 25. typical drive currents source (v ddext )voltage?v 03.5 0.5 1.0 1.5 2.0 2.5 3.0 s o u r c e ( v d d e x t ) c u r r e n t ? m a ?100 ?80 ?60 ?40 ?20 0 20 40 60 4.0 v ddext =3.3v@ +25c v ddext =3.0v@ +85c v oh v ol v ddext =3.0v@ +85c v ddext =3.3v@ +25c v ddext =3.65v@ ? 40c input current output current v ddext = 3.65v @ ?40c p ext oc v dd 2 f = table 23. p ext calculation example pin type # of pins % switching c f vdd2 = p ext address 15 50 10 pf 20 mhz 10.9 v = 0.01635 w msx 10 10pf 20 mhz 10.9 v = 0.0 w wr 1? 10pf 40 mhz 10.9 v = 0.00436 w data 16 50 10 pf 20 mhz 10.9 v = 0.01744 w clkout 1 ? 10 pf 80 mhz 10.9 v = 0.00872 w p ext =0.04687 w p total p = ext p int +
?41? rev. a adsp-2191m the output disable time t dis is the difference between t measured and t decay as shown in figure 26 . the time t measured is the interval from when the reference signal switches to when the output voltage decays ?v from the measured output high or output low voltage. the t decay is calculated with test loads c l and i l , and with ?v equal to 0.5 v. output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. the output enable time t ena is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram ( figure 26 ). if multiple pins (such as the data bus) ar e enabled, the measurement value is that of the first pin to start driving. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation at output disable time on page 40 . choose ?v to be the difference between the adsp-2191m?s output voltage an d the input threshold for the device requiring the hold time. a typical ?v will be 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or three-state current (per data line). the hold time will be t decay plus the minimum disable time (i.e., t datrwh for the write cycle). capacitive loading output delays and holds are based on standard capacitive loads: 50 pf on all pins (see figure 30 ). the delay and hold specifica- tions given should be derated by a factor of 1.5 ns/50 pf for loads other than the nominal value of 50 pf. figure 28 and figure 29 show how output rise time varies with capacitance. these figures also show graphically how output delays and holds vary with load capacitance. (note that this grap h or derating does not apply to output disable delays; see o u t p u t d i s a b l e t i m e o n p a g e 4 0 .) the graphs in these figures may no t be linear outside the ranges shown. environmental conditions the thermal characteristics in which the dsp is operating influence performance. thermal characteristics the adsp-2191m comes in a 144-lead lqfp or 144-lead ball grid array (mini-bga) package. the adsp-2191m is specified for an ambient temperature (t amb ) as calculated using the formula below. figure 26. output enable/disable figure 27. equivalent device loading for ac measurements (inclu des all fixtures) figure 28. voltage re ference levels for ac measurements (except ou tput enable/disable) t decay c l v ? i l --------------- = reference signal t dis output starts driving v oh (measured) ? v2.0v v ol (measured) + v1.0v t measured v oh (measured) v ol (measured) high impedance state. test conditions cause this voltage to be approximately 1.5v output stops driving t decay t ena 1.5v 50pf to output pin i ol i oh input or output 1.5v 1.5v figure 29. typical output rise time (10%-90%, v ddext = minimum at maximu m ambient operating temperature) vs. load capacitance 40 0 30 20 10 load capacitance ? pf 0250 50 100 150 200 r i s e a n d f a l l t i m e s ? n s ( 1 0 % ? 9 0 % ) fall time rise time
adsp-2191m ?42? rev. a to ensure that the t amb data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. a heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive. where: ? t amb = ambient temperature (measured near top surface of package) ? pd = power dissipation in w (this value depends upon the specific application; a me thod for calculating pd is shown under power dissipation). ? ca = value from table 24 . ? for the lqfp package: jc = 0.96c/w for the mini-bga package: jc = 8.4c/w figure 30. typical output delay or hold vs. load capacitance (at maximu m case temperature) load capacitance ? pf ?10 0250 50 100 150 200 30 20 10 0 o u t p u t d e l a y o r h o l d ? n s table 24. airflow (linear ft./min.) 0 100 200 400 600 airflow (meters/second) 00.5123 lqfp: ca (c/w) 44.3 41.4 38.5 35.3 32.1 mini-bga: ca (c/w) 26 24 22 20.9 19.8 t amb t case = pd ca ?
?43? rev. a adsp-2191m 144-lead lqfp pinout table 25 lists the lqfp pinout by signal name. table 26 lists the lqfp pinout by pin. table 25. 144-lead lqfp pins (alphabetically by signal) signal pin no. signal pin no. signal pin no. signal pin no. signal pin no. a0 84 bypass 72 gnd 33 hcms 27 tclk1 65 a1 85 clkin 132 gnd 54 hcioms 28 tclk2 47 a2 86 clkout 130 gnd 55 hrd 31 tdi 75 a3 87 d0 123 gnd 77 hwr 32 tdo 74 a4 88 d1 124 gnd 80 ioms 114 tfs0 59 a5 89 d2 125 gnd 94 ms0 115 tfs1 66 a6 91 d3 126 gnd 105 ms1 116 tfs2 48 a7 92 d4 128 gnd 129 ms2 117 tmr0 43 a8 93 d5 135 gnd 134 ms3 119 tmr1 44 a9 95 d6 136 ha16 23 opmode 83 tmr2 45 a10 96 d7 137 hack 26 pf0 34 tms 76 a11 97 d8 138 hack_p 24 pf1 35 trst 79 a12 98 d9 139 had0 3 pf2 36 txd 53 a13 99 d10 140 had1 4 pf3 37 v ddext 13 a14 101 d11 141 had2 6 pf4 38 v ddext 25 a15 102 d12 142 had3 7 pf5 39 v ddext 40 a16 103 d13 144 had4 8 pf6 41 v ddext 63 a17 104 d14 1 had5 9 pf7 42 v ddext 90 a18 106 d15 2 had6 10 rclk0 61 v ddext 100 a19 107 dr0 60 had7 11 rclk1 68 v ddext 118 a20 108 dr1 67 had8 12 rclk2 50 v ddext 131 a21 109 dr2 49 had9 14 rd 122 v ddext 143 ack 120 dt0 56 had10 15 reset 73 v ddint 19 bg 111 dt1 64 had11 17 rfs0 62 v ddint 58 bgh 110 dt2 46 had12 18 rfs1 69 v ddint 82 bmode0 70 emu 81had13 20rfs2 51v ddint 127 bmode1 71 gnd 5 had14 21 rxd 52 wr 121 bms 113 gnd 16 had15 22 tck 78 xtal 133 br 112 gnd 29 hale 30 tclk0 57
adsp-2191m ?44? rev. a table 26. 144-lead lqfp pins (n umerically by pin number) pin no. signal pin no. signal pin no. signal pin no. signal pin no. signal 1 d14 30 hale 59 tfs0 88 a4 117 ms2 2 d15 31 hrd 60 dr0 89 a5 118 v ddext 3had0 32 hwr 61 rclk0 90 v ddext 119 ms3 4 had1 33 gnd 62 rfs0 91 a6 120 ack 5gnd 34pf0 63v ddext 92 a7 121 wr 6 had2 35 pf1 64 dt1 93 a8 122 rd 7 had3 36 pf2 65 tclk1 94 gnd 123 d0 8 had4 37 pf3 66 tfs1 95 a9 124 d1 9 had5 38 pf4 67 dr1 96 a10 125 d2 10 had6 39 pf5 68 rclk1 97 a11 126 d3 11 had7 40 v ddext 69 rfs1 98 a12 127 v ddint 12 had8 41 pf6 70 bmode0 99 a13 128 d4 13 v ddext 42 pf7 71 bmode1 100 v ddext 129 gnd 14 had9 43 tmr0 72 bypass 101 a14 130 clkout 15 had10 44 tmr1 73 reset 102 a15 131 v ddext 16 gnd 45 tmr2 74 tdo 103 a16 132 clkin 17 had11 46 dt2 75 tdi 104 a17 133 xtal 18 had12 47 tclk2 76 tms 105 gnd 134 gnd 19 v ddint 48 tfs2 77 gnd 106 a18 135 d5 20 had13 49 dr2 78 tck 107 a19 136 d6 21 had14 50 rclk2 79 trst 108 a20 137 d7 22 had15 51 rfs2 80 gnd 109 a21 138 d8 23 ha16 52 rxd 81 emu 110 bgh 139 d9 24 hack_p 53 txd 82 v ddint 111 bg 140 d10 25 v ddext 54 gnd 83 opmode 112 br 141 d11 26 hack 55 gnd 84 a0 113 bms 142 d12 27 hcms 56 dt0 85 a1 114 ioms 143 v ddext 28 hcioms 57 tclk0 86 a2 115 ms0 144 d13 29 gnd 58 v ddint 87 a3 116 ms1
?45? rev. a adsp-2191m 144-lead mini-bga pinout table 27 lists the mini-bga pinout by signal name. table 28 lists the mini-bga pinout by ball number. table 27. 144-lead mini-bga pins (alphabetically by signal) signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. a0 j11 bypass m11 gnd f7 hale j1 tclk0 j6 a1 h9 clkin a5 gnd f8 hcioms j3 tclk1 m9 a2 h10 clkout c6 gnd f9 hcms h1 tclk2 k5 a3 g12 d0 d7 gnd g4 hrd j2 tdi k12 a4 h11 d1 a7 gnd g5 hwr k2 tdo l11 a5 g10 d2 c7 gnd g6 ioms e8 tfs0 m8 a6 f12 d3 a6 gnd h5 ms0 d9 tfs1 j8 a7 g11 d4 b7 gnd l6 ms1 a9 tfs2 m5 a8 f10 d5 a4 gnd m1 ms2 c9 tmr0 k4 a9 f11 d6 c5 gnd m12 ms3 d8 tmr1 l4 a10 e12 d7 b5 hack h3 opmode h12 tmr2 j4 a11 e11 d8 d5 hack_p g1 pf0 k1 tms k10 a12 e10 d9 a3 had0 c1 pf1 l1 trst j12 a13 e9 d10 c4 had1 b3 pf2 m2 txd m7 a14 d11 d11 b4 had2 c2 pf3 l2 v ddext e5 a15 d10 d12 c3 had3 d1 pf4 m3 v ddext e6 a16 d12 d13 a2 had4 d4 pf5 l3 v ddext f5 a17 c11 d14 b1 had5 d3 pf6 k3 v ddext f6 a18 c12 d15 b2 had6 d2 pf7 m4 v ddext g7 a19 b12 dr0 l7 had7 e1 rclk0 k7 v ddext g8 a20 b11 dr1 k9 had8 e4 rclk1 j9 v ddext h7 a21 a11 dr2 l5 had9 e2 rclk2 j5 v ddext h8 ack a8 dt0 h6 had10 f1 rd b8 v ddint d6 bg c10 dt1 l8 had11 e3 reset l12 v ddint f4 bgh b10 dt2 h4 had12 f2 rfs0 k8 v ddint g9 bmode0 l10 emu j10 had13 g2 rfs1 m10 v ddint j7 bmode1 l9 gnd a1 had14 f3 rfs2 m6 wr c8 bms a10 gnd a12 had15 g3 rxd k6 xtal b6 br b9 gnd e7 ha16 h2 tck k11
adsp-2191m ?46? rev. a table 28. 144-lead mini-bga pins (numerically by ball number) ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal a1 gnd c6 clkout e11 a11 h4 dt2 k9 dr1 a2 d13 c7 d2 e12 a10 h5 gnd k10 tms a3 d9 c8 wr f1 had10 h6 dt0 k11 tck a4 d5 c9 ms2 f2 had12 h7 v ddext k12 tdi a5 clkin c10 bg f3 had14 h8 v ddext l1 pf1 a6 d3 c11 a17 f4 v ddint h9 a1 l2 pf3 a7 d1 c12 a18 f5 v ddext h10 a2 l3 pf5 a8 ack d1 had3 f6 v ddext h11 a4 l4 tmr1 a9 ms1 d2 had6 f7 gnd h12 opmode l5 dr2 a10 bms d3 had5 f8 gnd j1 hale l6 gnd a11 a21 d4 had4 f9 gnd j2 hrd l7 dr0 a12 gnd d5 d8 f10 a8 j3 hcioms l8 dt1 b1 d14 d6 v ddint f11 a9 j4 tmr2 l9 bmode1 b2 d15 d7 d0 f12 a6 j5 rclk2 l10 bmode0 b3 had1 d8 ms3 g1 hack_p j6 tclk0 l11 tdo b4 d11 d9 ms0 g2 had13 j7 v ddint l12 reset b5 d7 d10 a15 g3 had15 j8 tfs1 m1 gnd b6 xtal d11 a14 g4 gnd j9 rclk1 m2 pf2 b7 d4 d12 a16 g5 gnd j10 emu m3 pf4 b8 rd e1 had7 g6 gnd j11 a0 m4 pf7 b9 br e2 had9 g7 v ddext j12 trst m5 tfs2 b10 bgh e3 had11 g8 v ddext k1 pf0 m6 rfs2 b11 a20 e4 had8 g9 v ddint k2 hwr m7 txd b12 a19 e5 v ddext g10 a5 k3 pf6 m8 tfs0 c1 had0 e6 v ddext g11 a7 k4 tmr0 m9 tclk1 c2 had2 e7 gnd g12 a3 k5 tclk2 m10 rfs1 c3 d12 e8 ioms h1 hcms k6 rxd m11 bypass c4 d10 e9 a13 h2 ha16 k7 rclk0 m12 gnd c5 d6 e10 a12 h3 hack k8 rfs0
?47? rev. a adsp-2191m outline dimensions 144-lead metric thin plasti c quad flatpack [lqfp] (st-144) 144-ball mini-bga [pbga] (ca-144-2) seating plane 1.60 max 0.15 0.05 0.08 max (lead coplanarity) 0.75 0.60 0.45 1.45 1.40 1.35 0.27 0.22 0.17 typ 0.50 bsc typ (lead pitch) 1 36 37 73 72 108 144 109 top view (pins down) 22.00 bsc sq 20.00 bsc sq dimensions are in millimeters and comply with jedec standard ms-026-bfb. actual position of each lead is within 0.08 of its ideal position, when measured in the lateral direction. center dimensions are nominal. notes: 3. 2. 1. detail a detail a pin 1 indicator seating plane 0.85 min 0.25 min dimensions are in millimeters and comply with jedec standard mo-205-ac. actual position of the ball grid is within 0.15 of its ideal position, relative to the package edges. actual position of each ball is within 0.08 of its ideal position, relative to the ball grid. center dimensions are nominal. notes: 3. 4. 1. 2. detail a 0.55 0.50 0.45 (ball diameter) 0.10 max (ball coplanarity) 1.70 max detail a 8.80 bsc sq 0.80 bsc (ball pitch) a b c d e f g h j k l m 121110987654321 10.00 bsc sq bottom view top view pin a1 indicator
adsp-2191m ?48? rev. a printed in u.s.a. c02936?0?7/02(a) ordering guide revision history part number 1, 2 1 st = plastic thin quad flatpack (lqfp). 2 ca = mini ball grid array (pbga) ambient temperature range instruction rate (mhz) package description operating voltage adsp-2191mkst-160 0oc to 70oc 160 144-lead lqfp 2.5 int./3.3 ext. v adsp-2191mbst-140 ?40oc to +85oc 140 144-lead lqfp 2.5 int./3.3 ext. v adsp-2191mkca-160 0oc to 70oc 160 144-ba ll mini-bga 2.5 int./3.3 ext. v adsp-2191mbca-140 ?40oc to +85oc 140 144- ball mini-bga 2.5 int./3.3 ext. v location page 7/02?changed from rev. 0 to rev. a changes to formatting only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . global

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